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SN54ABT374, SN74ABT374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997
D
D
D
D
D
D
State-of-the-Art
EPIC-
ΙΙ
B
™
BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25°C
High-Drive Outputs (–32-mA I
OH
, 64-mA I
OL
)
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
SN54ABT374 . . . J OR W PACKAGE
SN74ABT374A . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54ABT374 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
V
CC
2D
2Q
3Q
3D
4D
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the SN54ABT374 and
SN74ABT374A are edge-triggered D-type
flip-flops. On the positive transition of the clock
(CLK) input, the Q outputs are set to the logic
levels set up at the data (D) inputs.
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
8Q
8D
7D
7Q
6Q
6D
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data
can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT374 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT374A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
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4Q
GND
CLK
5Q
5D
1
SN54ABT374, SN74ABT374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
H
CLK
↑
↑
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
logic symbol
†
1
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
11
3
4
7
8
13
14
17
18
EN
C1
1D
2
5
6
9
12
15
16
19
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
1
CLK
11
C1
2
1D
3
1D
1Q
To Seven Other Channels
2
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SN54ABT374, SN74ABT374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V
O
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, I
O
: SN54ABT374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT374A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance,
θ
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT374
MIN
VCC
VIH
VIL
VI
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Outputs enabled
–55
0
4.5
2
0.8
VCC
–24
48
5
125
–40
0
MAX
5.5
SN74ABT374A
MIN
4.5
2
0.8
VCC
–32
64
5
85
MAX
5.5
UNIT
V
V
V
V
mA
mA
ns/V
°C
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
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3
SN54ABT374, SN74ABT374A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5 V,
VCC = 4 5 V
4.5
VOL
Vhys
II
IOZH
IOZL
Ioff
ICEX
IO§
ICC
VCC = 4 5 V
4.5
TEST CONDITIONS
II = –18 mA
IOH = –3 mA
IOH = –3 mA
IOH = –24 mA
IOH = –32 mA
IOL = 48 mA
IOL = 64 mA
100
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 0,
VCC = 5.5 V,
VCC = 5.5 V,
VI = VCC or GND
VO = 2.7 V
VO = 0.5 V
VI or VO
≤
4.5 V
VO = 5.5 V
VO = 2.5 V
Outputs high
–50
Outputs high
VCC = 5.5 V, IO = 0
55V
0,
VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
3.5
6.5
Outputs low
Outputs disabled
–100
±1
10‡
–10‡
±100
50
–180
250
30
250
1.5
–50
50
–180
250
30
250
1.5
–50
±1
10‡
–10‡
±1
10‡
–10‡
±100
50
–180
250
30
250
1.5
TA = 25°C
MIN TYP†
MAX
–1.2
2.5
3
2
2*
0.55
0.55*
0.55
0.55
2.5
3
2
2
V
mV
µA
µA
µA
µA
µA
mA
µA
mA
µA
mA
pF
pF
SN54ABT374
MIN
MAX
–1.2
2.5
3
V
SN74ABT374A
MIN
MAX
–1.2
UNIT
V
VOH
∆I
CC¶
Ci
Co
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ This data sheet limit may vary among suppliers.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT374
VCC = 5 V,
TA = 25°C
MIN
fclock
tw
tsu
th
Clock frequency
Pulse duration
Setup time before CLK↑
Hold time after CLK↑
CLK high or low
Data high
Data low
Data high or low
0
3.3
2
2
2
MAX
150
0
3.3
2.5
2.5
2.5
150
MHz
ns
ns
ns
MIN
MAX
UNIT
4
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