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74ABT373 Octal Transparent Latch with 3-STATE Outputs
March 2007
74ABT373
Octal Transparent Latch with 3-STATE Outputs
Features
■
3-STATE outputs for bus interfacing
■
Output sink capability of 64mA, source capability of
■
■
■
■
■
■
■
tm
General Description
The ABT373 consists of eight latches with 3-STATE
outputs for bus organized system applications. The flip-
flops appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup times is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH the
bus output is in the high impedance state.
32mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50pF and 250pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High-impedance, glitch-free bus loading during entire
power up and power down
Nondestructive, hot-insertion capability
Ordering Information
Order Number
74ABT373CSC
74ABT373CSJ
74ABT373CMSA
74ABT373CMTC
Package
Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-STATE Latch Outputs
Description
©1993 Fairchild Semiconductor Corporation
74ABT373 Rev. 1.4
www.fairchildsemi.com
74ABT373 Octal Transparent Latch with 3-STATE Outputs
Functional Description
The ABT373 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When
LE is LOW, the latches store the information that was
present on the D inputs at setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are in the bi-state mode. When OE is
HIGH the buffers are in the high impedance mode but
this does not interfere with entering new data into the
latches.
Truth Table
Inputs
LE
H
H
L
X
Output
D
n
H
L
X
X
OE
L
L
L
H
O
n
H
L
O
n
(no change)
Z
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
HIGH Impedance State
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1993 Fairchild Semiconductor Corporation
74ABT373 Rev. 1.4
www.fairchildsemi.com
2
74ABT373 Octal Transparent Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
T
STG
T
A
T
J
V
CC
V
IN
I
IN
V
O
Storage Temperature
Parameter
Ambient Temperature Under Bias
Junction Temperature Under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage
(1)
Input Current
(1)
Voltage Applied to Any Output
Disabled or Power-Off State
HIGH State
Current Applied to Output in LOW State (Max.)
DC Latchup Source Current Across Common Operating Range
OE Pin
Other Pins
Over Voltage Latchup (I/O)
Rating
–65°C to +150°C
–55°C to +125°C
–55°C to +150°C
–0.5V to +7.0V
–0.5V to +7.0V
–30mA to +5.0mA
–0.5V to +5.5V
–0.5V to V
CC
twice the rated I
OL
(mA)
–150mA
–500mA
10V
Note:
1. Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
T
A
V
CC
∆
V /
∆
t
Supply Voltage
Minimum Input Edge Rate
Data Input
Enable Input
Parameter
Free Air Ambient Temperature
Rating
–40°C to +85°C
+4.5V to +5.5V
50mV/ns
20mV/ns
©1993 Fairchild Semiconductor Corporation
74ABT373 Rev. 1.4
www.fairchildsemi.com
3
74ABT373 Octal Transparent Latch with 3-STATE Outputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input LOW Current
Input Leakage Test
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional
I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
Min.
2.0
Typ.
Max. Units
V
0.8
–1.2
V
V
V
0.55
1
1
7
–1
–1
µA
µA
V
10
–10
µA
µA
mA
µA
µA
µA
mA
µA
mA
mA
mA
mA/
MHz
V
µA
Min.
Min.
Min.
Max.
Max.
Max.
0.0
I
IN
=
–18mA
I
OH
=
–3mA
I
OH
=
–32mA
I
OL
=
64mA
V
IN
=
2.7V
(3)
V
IN
=
V
CC
V
IN
=
7.0V
V
IN
=
0.5V
(3)
V
IN
=
0.0V
I
ID
=
1.9µA, All Other Pins
Grounded
4.75
2.5
2.0
0–5.5V V
OUT
=
2.7V, OE
=
2.0V
0–5.5V V
OUT
=
0.5V, OE
=
2.0V
Max.
Max.
0.0
Max.
Max.
Max.
Max.
V
OUT
=
0.0V
V
OUT
=
V
CC
V
OUT
=
5.5V, All Others GND
All Outputs HIGH
All Outputs LOW
OE
=
V
CC
, All Others at V
CC
or Ground
V
I
=
V
CC
– 2.1V
Enable Input V
I
=
V
CC
– 2.1V
Data Input V
I
=
V
CC
– 2.1V,
All Others at V
CC
or Ground
Max.
Outputs OPEN, LE = V
CC
,
OE
=
GND
(2)
,
One-Bit Toggling,
50% Duty Cycle
–100
–275
50
100
50
30
50
2.5
2.5
2.5
0.12
I
CCD
Dynamic I
CC
No Load
(3)
Notes:
2. For 8-bit toggling, I
CCD
<
0.8mA/MHz.
3. Guaranteed, but not tested.
©1993 Fairchild Semiconductor Corporation
74ABT373 Rev. 1.4
www.fairchildsemi.com
4
stm32/stm8
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