HIGH-SPEED 3.3V
IDT70V9389/289L
64K x18/x16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features:
◆
◆
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT70V9389/289L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
LVTTL- compatible, single 3.3V (±0.3V) power supply
◆
◆
◆
◆
◆
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output
mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Flatpack (TQFP) and
100-pin Thin Quad Flatpack (TQFP)
Green parts available, see ordering information
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/
W
R
UB
R
CE
0R
CE
1L
LB
L
OE
L
1
0
0/1
1
0
0/1
CE
1R
LB
R
OE
R
FT
/PIPE
L
0/1
1b 0b
b a
1a 0a
0a 1a
a
0b 1b
b
0/1
FT
/PIPE
R
I/O
9L
-I/O
17L
(2)
I/O
Control
I/O
0L
-I/O
8L
(1)
I/O
Control
I/O
9R
-I/O
17R
(1)
I/O
0R
-I/O
8R
(1)
A
15L
A
0L
CLK
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
15R
A
0R
CLK
R
ADS
L
CNTEN
L
CNTRST
L
ADS
R
CNTEN
R
CNTRST
R
4856 drw 01
NOTES:
1. I/O
0X
- I/O
7X
for IDT70V9289.
2. I/O
8X
- I/O
15X
for IDT70V9289.
MARCH 2018
1
©2018 Integrated Device Technology, Inc.
DSC-4856/9
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Description:
The IDT70V9389/289 is a high-speed 64K x 18 (64K x 16) bit
synchronous Dual-Port RAM. The memory array utilizes Dual-Port
memory cells to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup and
hold times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
With an input data register, the IDT70V9389/289 has been
optimized for applications having unidirectional or bidirectional data
flow in bursts. An automatic power down feature, controlled by
CE
0
and CE
1,
permits the on-chip circuitry of each port to enter a very low
standby power mode. Fabricated using CMOS high-performance
technology, these devices typically operate on only 500mW of
power.
Pin Configuration
(1,2,3)
02/25/14
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
NC
NC
LB
R
UB
R
CE
0R
CE
1R
CNTRST
R
V
DD
V
SS
R/W
R
OE
R
FT/PIPE
R
V
SS
I/O
17R
I/O
16R
I/O
15R
I/O
14R
V
DD
V
DD
I/O
13R
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
NC
NC
NC
NC
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
NC
CNTEN
R
CLK
R
ADS
R
V
SS
V
DD
ADS
L
CLK
L
CNTEN
L
NC
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
70V9389PRF
PK128
(4)
128-Pin TQFP
Top View
(5)
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
NC
NC
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
V
DD
V
SS
R/W
L
OE
L
FT/PIPE
L
V
SS
I/O
17L
I/O
16L
I/O
15L
I/O
14L
V
DD
V
SS
I/O
13L
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O
12R
I/O
11R
V
SS
NC
I/O
10R
I/O
9R
I/O
8R
I/O
7R
V
DD
I/O
6R
I/O
5R
I/O
4R
V
SS
I/O
3R
V
DD
I/O
2R
I/O
1R
I/O
0R
V
SS
V
DD
I/O
0L
I/O
1L
V
SS
I/O
2L
I/O
3L
V
SS
I/O
4L
I/O
5L
I/O
6L
I/O
7L
V
DD
I/O
8L
I/O
9L
I/O
10L
NC
V
DD
I/O
11L
I/O
12L
4856 drw 02
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
INDEX
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
R/W
L
OE
L
V
DD
FT/PIPE
L
I/O
17L
I/O
16L
V
SS
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
70V9389PF
11
65
PN100
(4)
12
64
13
63
100-Pin TQFP
14
62
(5)
Top View
15
61
16
60
17
59
18
58
19
57
20
56
55
21
54
22
53
23
52
24
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CNTEN
L
CLK
L
ADS
L
V
SS
V
SS
ADS
R
CLK
R
CNTEN
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
02/25/14
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
LB
R
UB
R
CE
0R
CE
1R
CNTRST
R
R/W
R
V
SS
OE
R
FT/PIPE
R
I/O
17R
V
SS
I/O
16R
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
4856 drw 02a
,
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
9L
I/O
8L
V
DD
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
V
SS
I/O1
L
I/O
0L
V
SS
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
V
DD
I/O
7R
I/O
8R
I/O
9R
I/O
10R
6.42
3
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
NC
NC
LB
R
UB
R
CE
0R
CE
1R
CNTRST
R
V
DD
V
SS
R/W
R
OE
R
FT/PIPE
R
V
SS
I/O
15R
I/O
14R
I/O
13R
I/O
12R
V
DD
V
DD
I/O
11R
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
02/25/14
NC
NC
NC
NC
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
NC
CNTEN
R
CLK
R
ADS
R
V
SS
V
DD
ADS
L
CLK
L
CNTEN
L
NC
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
70V9289PRF
PK128
(4)
128-Pin TQFP
Top View
(5)
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
NC
NC
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
V
DD
V
SS
R/W
L
OE
L
FT/PIPE
L
V
SS
I/O
15L
I/O
14L
I/O
13L
I/O
12L
V
DD
V
SS
I/O
11L
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
I/O
10R
I/O
9R
V
SS
NC
I/O
8R
NC
NC
I/O
7R
V
DD
I/O
6R
I/O
5R
I/O
4R
V
SS
I/O
3R
V
DD
I/O
2R
I/O
1R
I/O
0R
V
SS
V
DD
I/O
0L
I/O
1L
V
SS
I/O
2L
I/O
3L
V
SS
I/O
4L
I/O
5L
I/O
6L
I/O
7L
V
DD
NC
NC
I/O
8L
NC
V
DD
I/O
9L
I/O
10L
4856 drw 02b
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
4
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
Index
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
NC
NC
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
V
DD
R/W
L
OE
L
FT/PIPE
L
V
SS
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
70
6
69
7
68
8
67
9
66
10
IDT70V9289PF
65
11
PN100
(4)
64
12
63
13
100-Pin TQFP
62
14
Top View
(5)
61
15
60
16
59
17
58
18
57
19
56
20
55
21
54
22
53
23
52
24
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CNTEN
L
CLK
L
ADS
L
V
SS
ADS
R
CLK
R
CNTEN
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
02/25/14
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
NC
NC
LB
R
UB
R
CE
0R
CE
1R
.
CNTRST
R
V
SS
R/W
R
OE
R
FT/PIPE
R
V
SS
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
4856 drw 02c
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
9L
I/O
8L
V
DD
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
V
SS
I/O
IL
I/O
0L
V
SS
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
V
DD
I/O
7R
I/O
8R
I/O
9R
NC
6.42
5
测评中心专版
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
