ICS8302-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
G
ENERAL
D
ESCRIPTION
The ICS8302-01 is a low skew, 1-to-2 LVCMOS/LVTTL
Fanout Buffer w/Complementary Output. The ICS8302-01
has a single ended clock input. The single ended clock
input accepts LVCMOS or LVTTL input levels.The
ICS8302-01 is characterizedat full 3.3V for input V
DD
,
and mixed 3.3V and 2.5V foroutput operating supply
modes (V
DDO
). Guaranteed output and part-to-part
skew characteristics make the ICS8302-01 ideal for
clock distribution applications demanding well defined
performance and repeatability.
F
EATURES
• Complementary LVCMOS / LVTTL output
• LVCMOS / LVTTL clock input accepts LVCMOS
or LVTTL input levels
• Maximum output frequency: 250MHz
• Output skew: 165ps (maximum)
• Part-to-part skew: 800ps (maximum)
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
B
LOCK
D
IAGRAM
Q
CLK
nQ
P
IN
A
SSIGNMENT
V
DDO
V
DD
CLK
GND
1
2
3
4
8
7
6
5
Q
GND
V
DDO
nQ
ICS8302-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
8302AM-01
www.idt.com
1
REV. A JULY 29, 2010
ICS8302-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6
2
3
4,7
5
8
Name
V
DDO
V
DD
CLK
GND
nQ
Q
Power
Power
Input
Power
Output
Output
Pulldown
Type
Description
Output supply pins.
Core supply pin.
LVCMOS / LVTTL clock input.
Power supply ground.
Complementary clock output. LVCMOS / LVTTL interface levels.
Clock output. LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
, V
DDO
= 3.465V
V
DD
= 3.465V, V
DDO
= 2.625V
22
16
51
51
7
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
pF
pF
KΩ
KΩ
Ω
8302AM-01
www.idt.com
2
REV. A JULY 29, 2010
ICS8302-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
13
4
Units
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
CLK
CLK
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
50
Ω
to V
DDO
/2
I
OH
= -100µA
50
Ω
to V
DDO
/2
I
OL
= 100µA
-5
2.6
2.9
0.5
0.2
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
V
V
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
IJ 133MHz
300
45
1.8
2.18
50
Test Conditions
Minimum
Typical
Maximum
250
2.7
165
800
800
55
60
Units
MHz
ns
ps
ps
ps
%
%
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
133MHz < ƒ
≤
250MHz
40
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8302AM-01
www.idt.com
3
REV. A JULY 29, 2010
ICS8302-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
T
ABLE
3C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
13
4
Units
V
V
mA
mA
T
ABLE
3D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
CLK
CLK
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
50
Ω
to V
DDO
/2
I
OH
= -100µA
50
Ω
to V
DDO
/2
I
OL
= 100µA
-5
1.8
2.2
0.5
0.2
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
V
V
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
IJ 133MHz
250
45
1.9
Test Conditions
Minimum
Typical
Maximum
250
2.9
250
900
650
55
60
Units
MHz
ns
ps
ps
ps
%
%
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
133MHz < ƒ
≤
250MHz
40
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8302AM-01
www.idt.com
4
REV. A JULY 29, 2010
ICS8302-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
DD
, V
DDO
= 1.65V±5%
2.05V±5% 1.25V±5%
SCOPE
LVCMOS
Qx
V
DD
V
DDO
SCOPE
Qx
LVCMOS
GND = -1.65V±5%
GND = -1.25V±5%
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
Q
DD
CLK
2
V
DDO
DDO
2
V
Q
nQ
V
2
DDO
nQ
DDO
2
2
t
PD
tsk(o)
P
ROPAGATION
D
ELAY
PART 1
Q
PART 2
Q
nQ
V
V
DD
O
UTPUT
S
KEW
2
V
DDO
80%
80%
2
Clock Outputs
DDO
20%
t
R
20%
t
F
2
tsk(pp)
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
nQ
V
DDO
V
DDO
2
Q
2
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
odc & t
P
ERIOD
8302AM-01
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5
REV. A JULY 29, 2010
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