74HCT9046A
Rev. 9 — 20 March 2020
PLL with band gap controlled VCO
Product data sheet
1. General description
The 74HCT9046A. This device features reduced input threshold levels to allow interfacing to TTL
logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to
interface inputs to voltages in excess of V
CC
.
2. Features and benefits
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Operation power supply voltage range from 4.5 V to 5.5 V
Low power consumption
Complies with JEDEC standard no. 7A
Inhibit control for ON/OFF keying and for low standby power consumption
Center frequency up to 17 MHz (typical) at V
CC
= 5.5 V
Choice of two phase comparators:
•
PC1: EXCLUSIVE-OR
•
PC2: Edge-triggered JK flip-flop
No dead zone of PC2
Charge pump output on PC2, whose current is set by an external resistor R
bias
Center frequency tolerance ±10 %
Excellent Voltage Controlled Oscillator (VCO) linearity
Low frequency drift with supply voltage and temperature variations
On-chip band gap reference
Glitch free operation of VCO, even at very low frequencies
Zero voltage offset due to operational amplifier buffering
ESD protection:
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HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
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3. Applications
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FM modulation and demodulation where a small center frequency tolerance is essential
Frequency synthesis and multiplication where a low jitter is required (e.g. video
picture-in-picture)
Frequency discrimination
Tone decoding
Data synchronization and conditioning
Voltage-to-frequency conversion
Motor-speed control
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HCT9046AD -40 °C to +125 °C
SO16
Description
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1
Nexperia
74HCT9046A
PLL with band gap controlled VCO
7. Functional description
The 74HCT9046A is a phase-locked-loop circuit that comprises a linear VCO and two different
phase comparators (PC1 and PC2) with a common signal input amplifier and a common
comparator input, see
Fig. 1.
The signal input can be directly coupled to large voltage signals
(CMOS level), or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias
input circuit keeps small voltage signals within the linear region of the input amplifiers. With a
passive low-pass filter, the 74HCT9046A forms a second-order loop PLL.
The principle of this phase-locked-loop is based on the familiar 74HCT4046A. However extra
features are built-in, allowing very high-performance phase-locked-loop applications. This is done,
at the expense of PC3, which is skipped in this 74HCT9046A. The PC2 is equipped with a current
source output stage here. Further a band gap is applied for all internal references, allowing a small
center frequency tolerance. The details are summed up in
Section 7.1.
If one is familiar with the
74HCT4046A already, it will do to read this section only.
7.1. Differences with respect to the familiar 74HCT4046A
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A center frequency tolerance of maximum ±10 %.
The on board band gap sets the internal references resulting in a minimal frequency shift at
supply voltage variations and temperature variations.
The value of the frequency offset is determined by an internal reference voltage of 2.5 V instead
of V
CC
- 0.7 V; In this way the offset frequency will not shift over the supply voltage range.
A current switch charge pump output on pin PC2_OUT allows a virtually ideal performance of
PC2; The gain of PC2 is independent of the voltage across the low-pass filter; Further a passive
low-pass filter in the loop achieves an active performance. The influence of the parasitic
capacitance of the PC2 output plays no role here, resulting in a true correspondence of the
output correction pulse and the phase difference even up to phase differences as small as a
few nanoseconds.
Because of its linear performance without dead zone, higher impedance values for the filter,
hence lower C-values, can be chosen; correct operation will not be influenced by parasitic
capacitances as in case of the voltage source output using the 74HCT4046A.
No PC3 on pin RB but instead a resistor connected to GND, which sets the load/unload
currents of the charge pump (PC2).
Extra GND pin 1 to allow an excellent FM demodulator performance even at 10 MHz and
higher.
Combined function of pin PC1_OUT/PCP_OUT. If pin RB is connected to V
CC
(no bias resistor
R
bias
) pin PC1_OUT/PCP_OUT has its familiar function viz. output of PC1. If at pin RB a
resistor (R
bias
) is connected to GND it is assumed that PC2 has been chosen as phase
comparator. Connection of R
bias
is sensed by internal circuitry and this changes the function of
pin PC1_OUT/PCP_OUT into a lock detect output (PCP_OUT) with the same characteristics as
PCP_OUT of pin 1 of the 74HCT4046A.
The inhibit function differs. For the 74HCT4046A a HIGH-level at the inhibit input (pin INH)
disables the VCO and demodulator, while a LOW-level turns both on. For the 74HCT9046A
a HIGH-level on the inhibit input disables the whole circuit to minimize standby power
consumption.
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7.2. VCO
The VCO requires one external capacitor C1 (between pins C1A and C1B) and one external
resistor R1 (between pins R1 and GND) or two external resistors R1 and R2 (between pins R1 and
GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO.
Resistor R2 enables the VCO to have a frequency offset if required (see
Fig. 4).
The high input impedance of the VCO simplifies the design of the low-pass filters by giving the
designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a
demodulator output of the VCO input voltage is provided at pin DEM_OUT. The DEM_OUT voltage
equals that of the VCO input. If DEM_OUT is used, a series resistor (R
s
) should be connected
from pin DEM_OUT to GND; if unused, DEM_OUT should be left open. The VCO output (pin
VCO_OUT) can be connected directly to the comparator input (pin COMP_IN), or connected via a
74HCT9046A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 9 — 20 March 2020
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