Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
ICS83940
G
ENERAL
D
ESCRIPTION
The ICS83940 is a low skew, 1-to-18 LVPECL-to-LVCMOS/
LVTTL Fanout Buffer. The ICS83940 has twoselectable
clock inputs. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The LVCMOS_CLK can accept
LVCMOS or LVTTL input levels. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω series
or parallel terminated transmission lines.
The ICS83940 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS83940 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
F
EATURES
•
Eighteen LVCMOS/LVTTL outputs, 16Ω typical output
impedance
•
Selectable LVCMOS_CLK or LVPECL clock inputs
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 250MHz
•
Output skew: 150ps (maximum)
•
Part to part skew: 750ps (maximum)
•
Full 3.3V or 2.5V supply modes
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Lead-Free package fully RoHS compliant
•
For New Designs Use: 83940DYLF or 83940DYILF
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
DDO
GND
Q0
Q1
Q2
Q3
Q4
Q5
CLK_SEL
PCLK
nPCLK
LVCMOS_CLK
GND
0
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q17
Q16
Q15
GND
Q14
Q13
Q12
V
DDO
24
23
22
21
20
19
18
17
Q6
Q7
Q8
V
DD
Q9
Q10
Q11
GND
18
Q0:Q17
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
1
ICS83940
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Pacakge
Top View
83940BY
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1
REV. B JANUARY 31, 2014
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 12, 17, 25
3
4
5
6
7, 21
8, 16, 29
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Name
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Power
Input
Input
Input
Input
Power
Power
Output
Type
Description
Power supply ground.
ICS83940
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
Pulldown input when HIGH. Selects PCLK, nPCLK inputs
when LOW. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup
Inver ting differential LVPECL clock input.
Core supply pins.
Output supply pins.
Clock outputs. 16
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldow
n refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
11
V
DD
, V
DDO
= 3.47
V
DD
, V
DDO
= 2.625
Test Conditions
Minimum
Typical
4
13
11
51
51
16
21
Maximum
Units
pF
pF
pF
KΩ
KΩ
Ω
T
ABLE
3A. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
Control Input
CLK_SEL
0
1
PCLK, nPCLK
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
0
0
0
0
0
1
1
LVCMOS_CLK
—
—
—
—
—
—
0
1
PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
—
—
nPCLK
1
0
Biased;
NOTE 1
Biased;
NOTE 1
0
1
—
—
Outputs
Q0:Q17
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Single Ended
Differential to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
Non Inver ting
Non Inver ting
NOTE 1: Please refer to the Application Information section. "Wiring the Differential Input to Accept Single Ended Levels".
83940BY
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2
REV. B JANUARY 31, 2014
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
ICS83940
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
DD
V
DDO
I
DD
I
DDO
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
25
25
Units
V
V
mA
mA
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
IH
V
IL
V
PP
V
CMR
I
IN
V
OH
Input High Voltage
Input Low Voltage
Peak-to-Peak
Input Voltage
Input Common Mode
Voltage; NOTE 1, 2
Input Current
Output High Voltage
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
PCLK, nPCLK
300
GND + 1.5
V
DD
±200
I
OH
= -20mA
2.4
0.5
Test Conditions
Minimum
2.4
Typical
Maximum
V
DD
0.8
Units
V
V
mV
V
µA
V
V
V
OL
Output Low Voltage
I
OL
= 20mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
83940BY
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3
REV. B JANUARY 31, 2014
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°
TO
70°
Symbol Parameter
f
MAX
Output Frequency
t
pLH
Propagation Delay;
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
Test Conditions
f
≤
150MHz
f
≤
150MHz
f
>
150MHz
f
>
150MHz
Measured on rising edge
@V
DDO
/2
f
<
150MHz
f
<
150MHz
f
>
150MHz
f
>
150MHz
Measured on rising edge
@V
DDO
/2
0.5 to 2.4V
0.5 to 2.4V
0.3
0.3
Minimum
Typical
ICS83940
Maximum
250
3.4
3.8
3.7
4
150
150
1.4
1.2
1.7
1.4
850
750
1.2
1.2
55
Units
MH z
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ps
ps
ns
ns
%
2
2.6
2
2.6
t
pLH
Propagation Delay;
t
sk(o)
t
sk(pp)
t
sk(pp)
t
sk(pp)
t
R
t
F
Output Skew;
NOTE 3, 5
Par t-to-Par t Skew;
NOTE 6
Par t-to-Par t Skew;
NOTE 6
Par t-to-Par t Skew;
NOTE 4, 5
Output Rise Time
Output Fall Time
odc
Output Duty Cycle
f
<
134MHz
45
50
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output V
DDO
/2.
NOTE 2: Measured from V
DD
/2 to V
DDO
/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages,
same temperature, and with equal load conditions. Using the same type of inputs on each device, the
outputs are measured at V
DDO
/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
DD
V
DDO
I
DD
I
DDO
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
25
25
Units
V
V
mA
mA
83940BY
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4
REV. B JANUARY 31, 2014
Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
T
ABLE
4D. DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
IH
V
IL
V
PP
V
CMR
I
IN
V
OH
Input High Voltage
Input Low Voltage
Peak-to-Peak
Input Voltage
Input Common Mode
Voltage; NOTE 1, 2
Input Current
Output High Voltage
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
PCLK, nPCLK
300
GND + 1.5
Test Conditions
Minimum
2
Typical
ICS83940
Maximum
V
DD
0.8
Units
V
V
mV
V
DD
±200
V
µA
V
V
I
OH
= -12mA
1.8
0.5
V
OL
Output Low Voltage
I
OL
= 12mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= 0°
TO
70°
Symbol Parameter
f
MAX
Output Frequency
t
pLH
Propagation Delay;
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
Test Conditions
f
≤
150MHz
f
≤
150MHz
f
>
150MHz
f
>
150MHz
Measured on rising edge
@V
DDO
/2
f
<
150MHz
f
<
150MHz
f
>
150MHz
f
>
150MHz
Measured on rising edge
@V
DDO
/2
0.5 to 1.8V
0.5 to 1.8V
0.3
0.3
Minimum
Typical
Maximum
200
4.6
4.4
4.4
4.4
200
200
2.6
1.7
2.2
1.7
1.2
1.0
1.2
1.2
55
Units
MH z
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
%
2
2.7
2.2
2.7
t
pLH
Propagation Delay;
t
sk(o)
t
sk(pp)
t
sk(pp)
t
sk(pp)
t
R
t
F
Output Skew;
NOTE 3, 5
Par t-to-Par t Skew;
NOTE 6
Par t-to-Par t Skew;
NOTE 6
Par t-to-Par t Skew;
NOTE 4, 5
Output Rise Time
Output Fall Time
odc
Output Duty Cycle
f
<
134MHz
45
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output V
DDO
/2.
NOTE 2: Measured from V
DD
/2 to V
DDO
/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages,
same temperature, and with equal load conditions. Using the same type of inputs on each device, the
outputs are measured at V
DDO
/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
83940BY
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5
REV. B JANUARY 31, 2014
stm32/stm8
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