Low Skew, 1-to-22 Differential-to-3.3V
LVPECL Fanout Buffer
Datasheet
8534-01
General Description
The 8534-01 is a low skew, 1-to-22 Differential-to-3.3V LVPECL
Fanout Buffer. The 8534-01 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input levels.
The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input
levels. The device is internally synchronized to eliminate runt pulses
on the outputs during asynchronous assertion/deassertion of the OE
pin. The 8534-01’s low output and part-to-part skew characteristics
make it ideal for workstation, server, and other high performance
clock distribution applications.
Features
•
•
•
•
•
•
•
•
•
•
•
Twenty-two differential LVPECL outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
PCLK, nPCLK supports the following input levels: LVPECL, CML,
SSTL
Maximum output frequency: 500MHz
Output skew: 100ps (maximum)
Translates any single-ended input signal (LVCMOS, LVTTL, GTL)
to LVPECL levels with resistor bias on nCLK input
Additive phase jitter, RMS): 0.15ps (typical)
Full 3.3V supply mode
0°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_SEL
Pullup
Pin Assignment
Q0
V
CCO
V
CCO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
nQ1
Q1
nQ0
Q3
nQ2
Q2
CLK
Pulldown
nCLK
Pullup/Pulldown
PCLK
Pulldown
nPCLK
Pullup/Pulldown
OE
Pullup
0
1
LE
Q
D
22
Q0:Q21
22
nQ0:nQ21
V
CCO
nc
nc
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
OE
nc
nc
nQ21
Q21
V
CCO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
V
CCO
Q14
nQ14
Q15
nQ15
Q16
nQ16
Q17
nQ17
Q18
nQ18
Q19
nQ19
Q20
nQ20
V
CCO
V
CCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
Q12
nQ12
Q13
nQ13
V
CCO
8534-01
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision C, December 1, 2015
8534-01 Datasheet
Pin Descriptions and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 16, 17, 32,
33, 48, 49, 64
2, 3, 12, 13
4
5
6
7
8
9
10
11
14, 15
18, 19
20, 21
22, 23
24, 25
26, 27
28, 29
30, 31
34, 35
36, 37
38, 39
40, 41
42, 43
44, 45
46, 47
50, 51
52, 53
54, 55
56, 57
58, 59
60, 61
62, 63
Name
V
CCO
nc
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
OE
nQ21, Q21
nQ20, Q20
nQ19, Q19
nQ18, Q18
nQ17, Q17
nQ16, Q16
nQ15, Q15
nQ14, Q14
nQ13, Q13
nQ12, Q12
nQ11, Q11
nQ10, Q10
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Unused
Power
Input
Input
Input
Input
Input
Power
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Pulldown
Pullup/
Pulldown
Pullup
Pulldown
Pullup/
Pulldown
Type
Description
Output supply pins for LVPECL outputs.
No connect.
Core supply pin for LVPECL outputs.
Non-inverting differential clock input.
Inverting differential clock input. Pulled to
2
/
3
V
CC
.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. Pulled to
2
/
3
V
CC
.
Negative supply pin.
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are disabled and drive differential low:
Qx = LOW, nQx = HIGH. LVCMOS / LVTTL interface levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
Differential clock outputs. LVPECL interface Levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2015 Integrated Device Technology, Inc.
2
Revision C, December 1, 2015
8534-01 Datasheet
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
37
75
Maximum
Units
pF
k
k
Function Table
Table 3. Control Input Function Table.
Inputs
OE
0
0
1
1
CLK_SEL
0
1
0
1
Outputs
Q0:Q21
LOW
LOW
CLK
PCLK
nQ0:nQ21
HIGH
HIGH
nCLK
nPCLK
Disabled
Enabled
nCLK, nPCLK
CLK, PCLK
OE
nQ0:nQ21
Q0:Q21
Figure 1. OE Timing Diagram
©2015 Integrated Device Technology, Inc.
3
Revision C, December 1, 2015
8534-01 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
22.3C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 85°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
230
Units
V
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE, CLK_SEL
OE, CLK_SEL
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
Units
V
V
µA
µA
©2015 Integrated Device Technology, Inc.
4
Revision C, December 1, 2015
8534-01 Datasheet
Table 4C. Differential DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 85°C
Symbol
I
IH
Parameter
CLK
Input High Current
nCLK
CLK
I
IL
V
PP
V
CMR
Input Low Current
nCLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.15
V
EE
+ 0.5
1.3
V
CC
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH.
Table 4C. LVPECL DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 85°C
Symbol
I
IH
Parameter
PCLK
Input High Current
nPCLK
PCLK
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Input Low Current
nPCLK
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.3
V
EE
+ 1.5
V
CCO
– 1.4
V
CCO
– 2.0
0.6
1.0
V
CC
V
CCO
– 0.9
V
CCO
– 1.7
1.0
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
V
V
V
NOTE 1: Common mode input voltage is defined as V
IH.
NOTE 2: Outputs terminated with 50
to V
CCO
– 2V.
©2015 Integrated Device Technology, Inc.
5
Revision C, December 1, 2015
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