LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-
LVDS FANOUT BUFFER
ICS889832
G
ENERAL
D
ESCRIPTION
The ICS889832 is a high speed 1-to-4 Differential-
to-LVDS Fanout Buffer and is a member of the
HiPerClockS™
HiPerClockS™ family of high performance clock
solutions from IDT. The ICS889832 is optimized
for high speed and very low output skew, making
it suitable for use in demanding applications such as SONET,
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The
internally terminated differential input and V
REF
_
AC
pin allow
other differential signal families such as LVPECL, LVDS, and
SSTL to be easily interfaced to the input with minimal use of
external components. The device also has an output enable
pin which may be useful for system test and debug purposes.
The ICS889832 is packaged in a small 3mm x 3mm 16-pin
VFQFN package which makes it ideal for use in space-
constrained applications.
F
EATURES
•
Four differential LVDS outputs
•
IN, nIN pair can accept the following differential input levels:
LVPECL, LVDS, SSTL
•
50Ω internal input termination to V
T
•
Output frequency: >2GHz
•
Output skew: 25ps (maximum)
•
Part-to-part skew: 200ps (maximum)
•
Additive phase jitter, RMS: <0.2ps (typical)
•
Propagation delay: 510ps (maximum)
•
2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
Q0
nQ0
IN
50Ω
P
IN
A
SSIGNMENT
nQ0
Q1 1
nQ1 2
Q2 3
16 15 14 13
12
11
10
9
5
Q3
V
DD
Q0
GND
IN
V
T
V
REF
_
AC
nIN
Q1
nQ1
50Ω
nQ2 4
6
nQ3
7
V
DD
8
EN
V
T
nIN
Q2
V
REF_AC
EN
D
Q
nQ2
ICS889832
16-Lead VFQFN
3mm x 3mm x 0.925 package body
K Package
Top View
Q3
nQ3
IDT
™
/ ICS
™
LVDS FANOUT BUFFER
1
ICS889832AK REV. A
OCTOBER 21,
2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 6
7, 14
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
V
DD
Type
Output
Output
Output
Power
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Positive supply pins.
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ
outputs will go HIGH on the next LOW transition at IN inputs. Input
threshold is V
DD
/2V. Includes a 37k
Ω
pull-up resistor. Default state is
HIGH when left floating. The internal latch is clocked on the falling edge
of the input signal IN. LVTTL / LVCMOS interface levels.
Inver ting differential clock input. 50
Ω
internal input termination to V
T
.
Reference voltage for AC-coupled applications.
Termination input.
Non-inver ting differential clock input. 50
Ω
internal input termination to V
T
.
Power supply ground.
8
EN
Input
Pullup
9
10
11
12
13
nIN
V
REF_AC
V
T
IN
GND
Input
Output
Input
Input
Power
15, 16
Q0, nQ0
Output
Differential output pair. LVDS interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
kΩ
IDT
™
/ ICS
™
LVDS FANOUT BUFFER
2
ICS889832AK REV. A
OCTOBER 21,
2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
EN
0
Q0:Q3
Disabled; LOW
Outputs
nQ0:nQ3
Disabled; HIGH
1
Enabled
Enabled
After EN switches, the clock outputs are disabled or enabled
following a falling input clock edge as shown in
Figur
e
1.
EN
V
DD
/2
t
S
t
H
V
DD
/2
nIN
IN
nQx
Qx
V
IN
→
t
PD
←
V
OUT
Swing
F
IGURE
1. EN T
IMING
D
IAGRAM
T
ABLE
3B. T
RUTH
T
ABLE
Inputs
IN
0
1
X
nIN
1
0
X
EN
1
1
0
0
0
1
(NOTE1)
Outputs
Q0:Q3
nQ0:nQ3
1
0
1
(NOTE1)
NOTE 1: On next negative transition of the input signal (IN).
IDT
™
/ ICS
™
LVDS FANOUT BUFFER
3
ICS889832AK REV. A
OCTOBER 21,
2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, TA
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
±50mA
±100mA
± 0.5mA
-40°C to +85°C
-65°C to 150°C
88.5°C/W (0 mps)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%; T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
120
Units
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%; T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
EN
EN
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
1.7
0
Typical
Maximum
V
DD
+ 0.3
0.7
5
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%; T
A
= -40°C
TO
85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
REF_AC
V
DIFF_IN
I
IN
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Reference Voltage
Differential Input Voltage Swing
Input Current; NOTE 1
(IN, nIN)
(IN, nIN)
(IN, nIN)
(IN, nIN)
Test Conditions
IN-to-VT
Minimum
40
1.2
0
0.15
V
DD
- 1.42
0.3
V
DD
- 1.37
Typical
50
Maximum
60
V
DD
V
IH
- 0.15
2.8
V
DD
- 1.32
3.4
35
Units
Ω
V
V
V
V
V
mA
NOTE 1: Guaranteed by design.
IDT
™
/ ICS
™
LVDS FANOUT BUFFER
4
ICS889832AK REV. A
OCTOBER 21,
2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%; T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1
1.25
Test Conditions
Minimum
0.3
Typical
0.4
Maximum
0.5
50
1.5
50
Units
mV
mV
V
mV
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%; T
A
= -40°C
TO
85°C
Symbol
f
MAX
Parameter
Maximum Output Frequency
Propagation Delay; (Differential);
NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
Clock Enable Setup Time
Clock Enable Hold Time
EN to IN, nIN
EN to IN, nIN
Integration Range:
12kHz - 20MHz
20% to 80%
70
300
300
Condition
Minimum
Typical
>2
275
390
510
25
200
<0.2
150
235
Maximum
Units
GHz
ps
ps
ps
ps
ps
ps
ps
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/t
F
t
S
t
H
All parameters are measured at
≤
1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
LVDS FANOUT BUFFER
5
ICS889832AK REV. A
OCTOBER 21,
2008
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