PCI Express
Jitter Attenuator
G
ENERAL
D
ESCRIPTION
The 874003 is a high performance Differential-to-LVDS Jitter
Attenuator designed for use in PCI Express systems. In some
PCI Express systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low bandwidth, high
phase noise PLL frequency synthesizer. In these systems, a jitter
attenuator may be required to attenuate high frequency random
and deterministic jitter components from the PLL synthesizer
and from the system board. The 874003 has 3 PLL bandwidth
modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will
provide maximum jitter attenuation, but with higher PLL tracking
skew and spread spectrum modulation from the motherboard
synthesizer may be attenuated. The 400kHz provides an
intermediate bandwidth that can easily track triangular spread
profiles, while providing good jitter attenuation. The 800kHz
bandwidth provides the best tracking skew and will pass most
spread profiles, but the jitter attenuation will not be as good
as the lower bandwidth modes. Because some 2.5Gb serdes
have x20 multipliers while others have than x25 multipliers, the
874003 can be set for 1:1 mode or 5/4 multiplication mode (i.e.
100MHz input/125MHz output) using the FSEL pins.
The 874003 uses IDT’s 3
rd
Generation FemtoClock
®
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
874003
DATA SHEET
F
EATURES
•
Three Differential LVDS output pairs
•
One Differential clock input
•
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 98MHz - 160MHz
•
Input frequency range: 98MHz - 128MHz
•
VCO range: 490MHz - 640MHz
•
Cycle-to-cycle jitter: 35ps (maximum)
•
3.3V operating supply
•
Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
•
0°C to 70°C ambient operating temperature
•
Available in lead-free RoHS compliant package
PLL B
ANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (default)
1 = PLL Bandwidth: ~800kHz
B
LOCK
D
IAGRAM
OEA Pullup
F_SELA Pulldown
BW_SEL Float
0 = ~200kHz
Float = ~400kHz
1 = ~800kHz
CLK Pulldown
nCLK Pullup
QA0
P
IN
A
SSIGNMENT
F_SELA
0 ÷5
(default)
1 ÷4
nQA0
QA1
Phase
Detector
VCO
490 - 640MHz
nQA1
874003
F_SELB
0 ÷5
(default)
1 ÷4
QB0
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
M = ÷5
(fixed)
nQB0
F_SELB Pulldown
MR Pulldown
OEB Pullup
G Package
Top View
874003 REVISION A 7/16/15
1
©2015 Integrated Device Technology, Inc.
874003 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 20
2, 19
3, 4
5
Name
QA1, nQA1
V
DDO
QA0, nQA0
MR
Power
Output
Input
Type
Output
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (nQXx) to go low and the inverted outputs
Pulldown
(QXx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Pullup/
PLL Bandwidth input. See Table 3B.
Pulldown
No connect.
Analog supply pin.
Pulldown
Frequency select pin for QAx/nQAx outputs.
LVCMOS/LVTTL interface levels.
Core supply pin.
Pullup
Output enable pin for QAx/nQAx pins. When HIGH, the QAx/nQAx out-
puts are active. When LOW, the QAx/nQAx outputs are in a high imped-
ance state. LVCMOS/LVTTL interface levels.
Inverting differential clock input.
Power supply ground.
Output enable pin for QB0 pins. When HIGH, the QB0/nQB0 outputs are
active. When LOW, the QB0/nQB0 outputs are in a high impedance state.
LVCMOS/LVTTL interface levels.
Frequency select pin for QB0/nQB0 outputs.
Pulldown
LVCMOS/LVTTL interface levels.
Pullup
Differential output pair. LVDS interface levels.
6
7
8
9
10
11
12
13
14
15
16
17, 18
BW_SEL
nc
V
DDA
F_SELA
V
DD
OEA
CLK
nCLK
GND
OEB
F_SELB
nQB0, QB0
Input
Unused
Power
Input
Power
Input
Input
Input
Power
Input
Input
Output
Pulldown Non-inverting differential clock input.
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Inputs
OEA
0
1
OEB
0
1
HiZ
Enabled
Outputs
QA0:1, nQA0:1
QB0/nQB0
HiZ
Enabled
T
ABLE
3B. PLL B
ANDWIDTH
/PLL B
YPASS
C
ONTROL
Inputs
PLL_BW
0
1
Float
PLL Band-
width
~200kHz
~800kHz
~400kHz
PCI EXPRESS
JITTER ATTENUATOR
2
REVISION A 7/16/15
874003 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
75
10
110
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
Parameter
Input High Voltage
OEA, OEB, MR,
F_SELA, F_SELB
BW_SEL
V
IL
V
IM
I
IH
Input Low Voltage
Input Mid Voltage
Input High Current
OEA, OEB, MR,
F_SELA, F_SELB
BW_SEL
BW_SEL
OEA, OEB
F_SELA, F_SELB
MR, BW_SEL
BW_SEL,
OEA, OEB
MR,
F_SELA, F_SELB
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
V
DD
/2 - 0.1
Test Conditions
Minimum
2
V
DD
- 0.4
-0.3
0.8
0.4
V
DD
/2 + 0.1
5
150
Typical
Maximum
V
DD
+ 0.3
Units
V
V
V
V
V
µA
µA
µA
µA
I
IL
Input Low Current
REVISION A 7/16/15
3
PCI EXPRESS
JITTER ATTENUATOR
874003 DATA SHEET
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
-150
0.15
GND + 0.5
1.3
V
DD
- 0.85
V
V
5
150
µA
Minimum
Typical
Maximum
150
Units
µA
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is V
DD
+ 0.3V.
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
275
1.2
Typical
375
1.35
Maximum
485
50
1.5
50
Units
mV
mV
V
mV
V
OS
Δ
V
OS
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
tjit(cc)
tsk(o)
t
R
/ t
F
odc
Parameter
Output Frequency
Cycle-to-Cycle Jitter, NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
275
48
Test Conditions
Minimum
98
Typical
Maximum
160
35
50
725
52
Units
MHz
ps
ps
ps
%
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
PCI EXPRESS
JITTER ATTENUATOR
4
REVISION A 7/16/15
嵌入式系统
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