3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
4. t
HZCS
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
5. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05272 Rev. **
Page 3 of 8
CYM1464
Switching Characteristics
Over the Operating Range (continued)
[3]
1464-35
Parameter
WRITE CYCLE
[5]
t
WC
t
SCS
t
AW
t
HA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[4]
35
30
30
3
25
20
2
0
15
45
40
40
3
35
25
3
0
15
55
50
50
3
40
35
3
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
1464-45
Min.
Max.
1464-55
Min.
Max.
Unit
Switching Waveforms
Read Cycle No. 1
[6,7]
t
RC
ADDRESS
t
AA
t
OHA
DATAOUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2
CS
[6,8]
t
RC
t
ACS
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
DATA OUT
t
LZCS
t
PU
V
CC
SUPPLY
CURRENT
50%
t
PD
ICC
50%
ISB
DATA VALID
t
HZOE
t
HZCS
HIGH
IMPEDANCE
Notes:
6. WE is HIGH for read cycle.
7. Device is continuously selected, CS = V
IL
.
8. Address valid prior to or coincident with CS transition LOW.
Document #: 38-05272 Rev. **
Page 4 of 8
CYM1464
Switching Waveforms
(continued)
Write Cycle No. 1 (WE Controlled)
[5]
t
WC
ADDRESS
t
SCS
CS
t
AW
t
SA
WE
t
SD
DATAIN
DATA VALID
t
HZWE
DATAI/O
DATA UNDEFINED
t
LZWE
HIGH IMPEDANCE
t
HD
t
PWE
t
HA
Write Cycle No. 2 (CS Controlled)
[5,9]
t
WC
ADDRESS
t
SA
CS
t
AW
WE
t
PWE
t
SD
DATAIN
DATA VALID
t
HZWE
DATAI/O
HIGH IMPEDANCE
DATA UNDEFINED
t
HD
t
HA
t
SCS
Note:
9. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
