LOW SKEW, 1-TO-16 LVCMOS/LVTTL
CLOCK GENERATOR
ICS87016I
Features
•
•
•
•
•
•
•
•
•
•
•
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Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock
input
CLK1, CLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK0 supports the following input types: LVCMOS, LVTTL
Maximum output frequency: 250MHz
Independent bank control for ÷1 or ÷2 operation
Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V
operation
Asynchronous clock enable/disable
Output skew: 170ps (maximum)
Bank skew: 50ps (maximum
Part-to-Part Skew: 800ps (maximum)
Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Description
The ICS87016I is a low skew, 1:16 LVCMOS/LVTTL
Clock Generator and is a member of the
HiPerClockS™
HiPerClockS family of High Performance Clock
Solutions. The device has 4 banks of 4 outputs and
each bank can be independently selected for
÷1
or
÷2
frequency operation. Each bank also has its own power supply
pins so that the banks can operate at the following different
voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω series or
parallel terminated transmission lines.
ICS
The divide select inputs, DIV_SELA:DIV_SELD, control the output
frequency of each bank. The output banks can be independently
selected for
÷1
or
÷2
operation. The bank enable inputs,
CLK_ENA:CLK_END, support enabling and disabling each bank
of outputs individually. The CLK_ENA:CLK_END circuitry has a
synchronizer to prevent runt pulses when enabling or disabling the
clock outputs. The master reset input, MR/OE, resets the
÷1/÷2
flip flops and also controls the active and high impedance states of
all outputs. This pin has an internal pull-up resistor and is normally
used only for test purposes or in systems which use low power
modes.
The ICS87016I is characterized to operate with the core at 3.3V or
2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank,
output, and part-to-part skew characteristics make the 87016I
ideal for those clock applications demanding well-defined
performance and repeatability.
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•
Block Diagram
MR/OE
D
CLK0
CLK1
CLK1
CLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
1
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
0
1
0
D
LE
Pin Assignment
V
DD
CLK1
CLK1
CLK_SEL
GND
QA0
V
DDOA
QA1
GND
QA2
V
DDOA
QA3
0
1
÷1
÷2
1
0
LE
4
QA0:QA3
V
DD
CLK0
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
MR/OE
GND
D
1
0
D
LE
LE
4
QB0:QB3
4
QC0:QC3
4
QD0:QD3
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
5
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
QD2
GND
QD1
V
DDOD
QD0
GND
QC3
V
DDOC
QC2
QD3
V
DDOD
GND
GND
QB0
V
DDOB
QB1
GND
QB2
V
DDOB
QB3
GND
QC0
V
DDOC
QC1
ICS87016I
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
1
ICS87016AYI REV. C MAY 25, 2007
IDT™ / ICS™
LVCMOS/LVTTL CLOCK GENERATOR
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 48
2
3
4
5
6
7
8
9
10
11
12, 16, 20,
24, 28, 32,
36, 40, 44
13, 15, 17, 19
14, 18
21, 23, 25, 27
22, 26
29, 31, 33, 35
30, 34
37, 39, 41, 43
38, 42
45
46
47
Name
V
DD
CLK0
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
MR/OE
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pulldown
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Type
Description
Positive supply pins.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Controls frequency division for Bank A outputs. See Table 3.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs. See Table 3.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank C outputs. See Table 3.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank D outputs. See Table 3.
LVCMOS / LVTTL interface levels.
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
Master reset. When LOW, resets the ÷1/÷2 flip flops and sets the outputs to
high impedance. LVCMOS / LVTTL interface levels.
Power supply ground
GND
QD3, QD2,
QD1, QD0
V
DDOD
QC3, QC2,
QC1, QC0
V
DDOC
QB3, QB2,
QB1, QB0
V
DDOB
QA3, QA2,
QA1, QA0
V
DDOA
CLK_SEL
CLK1
CLK1
Power
Output
Power
Output
Power
Output
Power
Output
Power
Input
Input
Input
Pulldown
Pullup
Pulldown
Bank D single-ended clock outputs. LVCMOS/LVTTL interface levels.
Bank D output supply pins.
Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels.
Bank C output supply pins.
Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels.
Bank B output supply pins.
Bank A single-ended clock outputs. LVCMOS/LVTTL interface levels.
Bank B output supply pins.
Clock select input. When HIGH, selects CLK1, CLK1 inputs.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
Inverting differential clock input.
Non-inverting differential clock input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
IDT™ / ICS™
LVCMOS/LVTTL CLOCK GENERATOR
2
ICS87016AYI REV. C MAY 25, 2007
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
V
DD,
V
DDOx
= 3.465V
V
DD,
V
DDOx
= 2.625V
Power Dissipation Capacitance
(per output); NOTE 1
V
DD
= 3.465V,
V
DDOx
= 2.625V
V
DD
= 3.465V,
V
DDOx
= 1.89V
V
DD
= 2.625V,
V
DDOx
= 1.89V
R
OUT
Output Impedance
5
7
Test Conditions
Minimum
Typical
4
51
51
18
12
20
30
14
12
Maximum
Units
pF
k
Ω
k
Ω
pF
pF
pF
pF
pF
C
PD
Ω
NOTE 1: V
DDOx
denotes V
DDOA,
V
DDOB,
V
DDOC,
V
DDOD.
Function Tables
Table 3. Function Table
Inputs
MR/OE
0
1
1
1
CLK_ENx
X
1
1
0
DIV_SELx
X
0
1
X
Bank [A:D]
Hi-Z
Active
Active
LOW
Outputs
Qx Frequency
N/A
fIN/2
fIN
N/A
IDT™ / ICS™
LVCMOS/LVTTL CLOCK GENERATOR
3
ICS87016AYI REV. C MAY 25, 2007
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD Ox
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDOx
= 3.3V ± 5%, 2.5V ± 5%, 1.8V ± 5%, T
A
= -40°C to
85°C
Symbol
V
DD
V
DDOA,
V
DDOB,
V
DDOC,
V
DDOD
I
DD
I
DDOA,
I
DDOB,
I
DDOC,
I
DDOD
Parameter
Positive Supply Voltage
Test Conditions
Minimum
3.135
3.135
Output Supply Voltage
2.375
1.71
Power Supply Current
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
1.89
100
Units
V
V
V
V
mA
Output Supply Current
15
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, V
DDOx
= 2.5V ± 5%, 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDOA,
V
DDOB,
V
DDOC,
V
DDOD
I
DD
I
DDOA,
I
DDOB,
I
DDOC,
I
DDOD
Parameter
Positive Supply Voltage
Test Conditions
Minimum
2.375
2.375
Output Supply Voltage
1.71
Power Supply Current
1.8
1.89
95
V
mA
Typical
2.5
2.5
Maximum
2.625
2.625
Units
V
V
Output Supply Current
8
mA
IDT™ / ICS™
LVCMOS/LVTTL CLOCK GENERATOR
4
ICS87016AYI REV. C MAY 25, 2007
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
Table 4C. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
Input Low Voltage
V
DD
= 3.465V
V
DD
= 2.625V
CLK0, CLK_SEL
I
IH
Input
High Current
CLK_EN[A:D],
DIV_SEL[A:D], MR/OE
CLK0, CLK_SEL
I
IL
Input
Low Current
CLK_EN[A:D],
DIV_SEL[A:D], MR/OE
V
DD
= V
IN
= 3.465V or
2.625V
V
DD
= V
IN
= 3.465V or
2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DDOx
= 3.3V ± 5%
V
OH
Output High Voltage; NOTE 1
V
DDOx
= 2.5V ± 5%
V
DDOx
= 1.8V ± 5%;
I
OH
= -2mA
V
DDOx
= 3.3V ± 5%
V
OL
Output Low Voltage; NOTE 1
V
DDOx
= 2.5V ± 5%
V
DDOx
= 1.8V ± 5%;
I
OH
= 2mA
I
OZL
I
OZH
Output Hi-Z Current Low
Output Hi-Z Current High
-5
5
-5
-150
2.6
1.8
V
DD
– 0.45
0.5
0.5
0.45
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
µA
µA
V
IL
NOTE 1: Outputs terminated with 50Ω to V
DDOX
/2. See Parameter Measurement Information,
Output Load Test Circuit diagrams.
Table 4D. Differential DC Characteristics,
T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
CLK1
Input High Current
CLK1
CLK1
I
IL
V
PP
V
CMR
Input Low Current
CLK1
Peak-to-Peak Voltage
Common Mode Input Voltage;
NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
-5
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
NOTE 2: For single-ended applications, the maximum input voltage for CLK1,
CLK1
is V
DD
+ 0.3V.
IDT™ / ICS™
LVCMOS/LVTTL CLOCK GENERATOR
5
ICS87016AYI REV. C MAY 25, 2007
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