Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
8-Bit 12-Ch I/O DAC
PT8146
DESCRIPTION
The PT8146 is an 8-bit D/A converter with 12 built-in channels. Each of the 12 analog outputs have a
built-in OP amplifier with large current drive capability. The data input/output format is chip select (/CS)
with serial bus connection available while a built-in 12-bit I/O expander enables serial-parallel
conversion (8 of the 12 bits can also be used for analog output).
FEATURES
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Ultra compact package
Ultra low power consumption (1.2mW/chl: typical)
Built-in 12-channel R-2R type 8-bit D/A converter
Built-in 12-bit I/O expander (8 bits also function as analog output)
Built-in analog output amplifier (sink current 1.0mA maximum, source current 1.0mA maximum)
Built-in power-on detection circuit (initialized at detection of VccD power-on)
MCU interface compatible with 3V to 5V systems
Power divided into MCU interface power supply (VccD) and OP amplifier power supply (VccA), D/A
converter power supply (VccD)
Analog output capability from 0 V to VccA
Serial data I/O operates to maximum of 2.5MHz (in cascade connection, up to 2.5MHz when
VccD=5V, up to 1.5Mhz when VccD=3V)
CMOS process
Available in 24 pin, SSOP Package
APPLICATIONS
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Microcontroller port expansion
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Electronic level adjustment
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Replacement of semi-fixed resistance for tuning
PT8146 V1.1
-1-
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
8-Bit 12-Ch I/O DAC
PT8146
PIN DESCRIPTION
Pin Name
AO1 to AO4
Description
Pin No.
D/A converter analog output pins (VDD to GND output).
1 to 4
(Default: output #00 setting level)
These pins may be used as either I/O expander parallel input/output
5 to 12
(VCCA/GND output 0.5 VCCA/0.2 VCCA input) or as D/A converter analog
output (VDD to GND output).
Pin status is controlled by input data.
See “Data Configuration”. (Default: Input mode, Hi-Z state)
D/A converter reference power pin.
13
MCU interface power supply pin (power supply for I/O expander)
14
I/O expander parallel input/output pins.
15 to 18
(VCCD/GND output: When VCCD
≥
4.0 V, 0.5 VCCD/0.2 VCCD input,
When VCCD < 4.0 V, 2 V/0.2 VCCD input)
Pin status is controlled by input data
See “Data Configuration.” (Default: Input mode, Hi-Z state)
Shift clock signal input pin.
19
When CS = “L”, SI data is loaded into the shift register at the rising edge of
the shift clock.
Data input pin (serial input pin).
20
Used for 16-bit serial data input.
Data output pin (serial output pin).
21
The first bit (LSB) data of the 16-bit shift register is output simultaneously
with the falling edge of the shift clock.
When /CS output = “H”, this pin goes to high impedance state.
Chip select signal input pin.
22
Input to shift registers is enabled when the/ CS signal falling edges. Shift
register contents can be executed when the /CS signal rising edges.
Analog unit power supply pin (OP amplifier power supply).
23
Common GND pin
24
D11/AO5 to
D4/AO12
VDD*1
VCCD*1
D3 to D0
CLK*2
SI*2
SO
/CS*2
VCCA*1
GND
*1: Be sure that VCCA
≥
VCCD, and that VCCA
≥
VDD.
*2: Do not leave this pin in floating state.
PT8146 V1.1
-4-
February, 2006
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