TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91C630
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
TMP91C630
CMOS 16-Bit Microcontrollers
TMP91C630F
1.
Outline and Features
TMP91C630 is a high-speed 16-bit microcontroller designed for the control of various mid- to
large-scale equipment. With 2 Kbytes of boot ROM included, it allows your programs to be erased
and rewritten on board.
TMP91C630 comes in a 100-pin flat package. Listed below are the features.
(1) High-speed 16-bit CPU (900/L1 CPU)
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Instruction mnemonics are upward-compatible with TLCS-90/900
16 Mbytes of linear address space
General-purpose registers and register banks
16-bit multiplication and division instructions; bit transfer and arithmetic instructions
Micro DMA: Four-channels (444 ns/2 bytes at 36 MHz)
(2) Minimum instruction execution time: 111 ns (at 36 MHz)
(3) Built-in RAM: 6 Kbytes
Built-in ROM: None
Built-in Boot ROM: 2 Kbytes
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TMP91C630
(4) External memory expansion
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Expandable up to 16 Mbytes (shared program/data area)
Can simultaneously support 8-/16-bit width external data bus
Dynamic data bus sizing
(5) 8-bit timers: 6 channels
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Event counter :2 channels
(6) 16-bit timer/event counter: 1 channel
(7) Serial bus interface: 2 channels
(8) 10-bit AD converter: 8 channels
(9) Watchdog timer
(10) Chip Select/Wait controller: 4 blocks
(11) Interrupts: 35 interrupts
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9 CPU interrupts: Software interrupt instruction and illegal instruction
19 internal interrupts: 7 priority levels are selectable.
7 external interrupts: 7 priority levels are selectable.
(Level mode, rising edge mode and falling edge mode are selectable.)
(12) Input/output ports: 53 pins
(13) Standby function
Three halt modes: Idle2 (programmable), Idle1, Stop
(14) Operating voltage
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VCC
=
2.7 V to 3.6 V (fc max
=
36 MHz)
100-pin QFP: P-LQFP100-1414-0.50F
(15) Package
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2005-11-15
TMP91C630
ADTRG
(AN3/PA3)
AN0~AN7 (PA0~PA7)
VREFH
VREFL
AVCC
AVSS
CPU (TLCS-900L1)
DVCC [4]
DVSS [4]
BOOT
10-bit 8-channel
AD
converter
Port A
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
B C
D E
H L
IX
IY
IZ
SP
32 bits
AM0/AM1
RESET
OSC
Clock gear
Port 1
Port 2
X1
X2
EMU0
EMU1
(P10~P17) D8~D15
(P20~P27) A16~A23
SR
RD
F
PC
WR
PZ2 (
HWR
)
PZ3
Port Z
Watchdog timer
(WDT)
Data bus
Address bus
Serial I/O
(channel 0)
Port 5
Serial I/O
(channel 1)
D0~D7
A0~A7
A8~A15
TXD0 (P80)
RXD0 (P81)
SCLK0/
CTS0
(P82)
STS0
(P83)
BUSRQ
(P53)
BUSAK
(P54)
TXD1 (P84)
RXD1 (P85)
SCK1/
CTS1
(P86)
STS1
(P87)
Port 8
WAIT
(P55)
TA0IN/INT1 (P70)
TA1OUT (P71)
8-bit timer
(TMRA0)
8-bit timer
(TMRA1)
6-KB RAM
8-bit timer
(TMRA2)
CS/WAIT
controller
(4-block)
CS0
(P60)
CS1
(P61)
CS2
(P62)
CS3
(P63)
Interrupt
controller
NMI
INT0 (P56)
TA3OUT/INT2 (P72)
8-bit timer
(TMRA3)
TB0IN0 (P93)
TB0IN1 (P94)
TB0OUT0 (P95)
TB0OUT1 (P96)
INT5 (P90)
TA4IN/INT3 (P73)
TA5OUT (P74)
INT4 (P75)
8-bit timer
(TMRA4)
8-bit timer
(TMRA5)
Port 7
2-KB boot ROM
16-bit timer
(TMRB0)
Port 9
Figure 1.1 TMP91C630 Block Diagram
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2005-11-15