TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91C824
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
**CAUTION**
How to release the HALT mode
Usually, interrupts can release all halts status. However, the interrupts
=
(
NMI
,
INT0 to INT3, INTRTC, INTALM0 to INTALM4), which can release the HALT
mode may not be able to do so if they are input during the period CPU is shifting
to the HALT mode (for about 5 clocks of f
FPH
) with IDLE1 or STOP mode (IDLE2
is not applicable to this case). (In this case, an interrupt request is kept on hold
internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficultly. The priority of this interrupt is
compare with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
TMP91C824
CMOS 16-Bit Microcontrollers
TMP91C824F/JTMP91C824-S
1.
Outline and Features
TMP91C824 is a high-speed 16-bit microcontroller designed for the control of various mid- to
large-scale equipment.
TMP91C824F comes in a 100-pin flat package. JTMP91C824-S is a chip form product.
Listed below are the features.
(1) High-speed 16-bit CPU (900/L1 CPU)
•
•
•
•
•
Instruction mnemonics are upward-compatible with TLCS-90
16 Mbytes of linear address space
General-purpose registers and register banks
16-bit multiplication and division instructions; bit transfer and arithmetic instructions
Micro DMA: 4 channels (485 ns/2 bytes at 33 MHz)
(2) Minimum instruction execution time: 121 ns (at 33 MHz)
(3) Built-in RAM: 8 Kbytes
Built-in ROM: None
91C824-1
2005-12-16
TMP91C824
(4) External memory expansion
•
•
•
Expandable up to 106 Mbytes (shared program/data area)
Can simultaneously support 8-/16-bit width external data bus
Dynamic data bus sizing
Separate bus system
(5) 8-bit timers: 4 channels
(6) General-purpose serial interface: 2 channels
•
•
•
•
UART/Synchronous mode: 2 channels
IrDA Ver.1.0 (115.2 kbps) mode selectable: 1 channel
I
2
C bus mode/clock synchronous mode selectable
Based on TC8521A
(7) Serial bus interface: 1 channel
(8) Timer for real-time clock (RTC)
(9) 10-bit AD converter: 8 channels
(10) Watchdog timer
(11) Melody/alarm generator
•
•
•
Melody: Output of clock 4 to 5461 Hz
Alarm: Output of the 8 kinds of alarm pattern
Output of the 5 kinds of interval interrupt
(12) Chip select/wait controller: 4 channels
(13) Memory management unit
•
•
•
•
Expandable up to 106 Mbytes (4 local areas/8-bank method)
9 CPU interrupts:
Software interrupt instruction and illegal instruction
(14) Interrupts: 37 interrupts
23 internal interrupts: 7 priority levels are selectable
5 external interrupts: 7 priority levels are selectable
(among 4 interrupts are selectable edge mode)
(15) Input/output ports: 35 pins (at external 16-bit data bus memory)
(16) Standby function
Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP
(17) Triple-clock controller
•
•
•
•
•
•
•
Clock doubler (DFM) circuit is inside
Clock gear function: Select a high-frequency clock fc/1 to fc/16
Slow mode (fs
=
32.768 kHz)
V
CC
=
2.7 V to 3.6 V (fc max
=
33 MHz)
V
CC
=
1.8 V to 3.6 V (fc max
=
10 MHz)
100-pin QFP: P-LQFP100-1414-0.50F
Chip form supply also available. For details, contact your local Toshiba sales
representative.
(18) Operating voltage
(19) Package
91C824-2
2005-12-16
TMP91C824
ADTRG
(P83)
DVCC [2]
10-bit 8-channel
AD
converter
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
B C
D E
H L
IX
IY
IZ
SP
32 bits
SR
F
AN0 to AN7 (P80 to P87)
AVCC, AVSS
VREFH, VREFL
TXD0 (PC0)
RXD0 (PC1)
SCLK0/
CTS0
(PC2)
TXD1 (PC3)
RXD1 (PC4)
SCLK1/
CTS1
(PC5)
OPTRX0, SCK (P70)
OPTTX0, SO/SDA(P71)
SI/SCL (P72)
TA0IN (PB0)
DVSS [2]
X1
H-OSC
X2
Clock gear,
Clock doubler
L-OSC
XT2
SCOUT (PD5)
EMU0
EMU1
XT1
SIO/UART/IrDA
(SIO0)
SIO/UART
(SIO1)
RESET
AM0
AM1
Serial bus
I/F(SBI)
D0 to D7
A0 to A7
A8 to A15
8-bit timer
(TMRA0)
8-bit timer
(TMRA1)
8-bit timer
(TMRA2)
Port 1
P10 to P17 (D8 to D15)
TA1OUT (PB1)
Port 2
P20 to P27 (A16 to A23)
RD
TA3OUT (PB2)
8-bit timer
(TMRA3)
Port 6
WDT
(Watchdog timer)
Port Z
WR
HWR
(PZ2)
R/
W
(PZ3)
BUSRQ
(P54)
Port 5
BUSAK
(P55)
WAIT
(P56)
Port 8
8-Kbyte RAM
CS/WAIT
controller
(4 blocks)
CS0
to
CS3
(P60 to P63),
CS2A
to
CS2E
(P62, P64 to P67)
(P60 to P67)
MMU
Port B
Port C
Port D
Interrupt
controller
Melody/
Alarm-out
NMI
INT0 to INT3 (PB3 to PB6)
MLDALM (PD7)
RTC
ALARM
,
MLDALM
(PD6)
( ): Initial function after reset
Figure 1.1 TMP91C824 Block Diagram
91C824-3
2005-12-16
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