54F 74F544 Octal Registered Transceiver
December 1994
54F 74F544
Octal Registered Transceiver
General Description
The ’F544 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either direc-
tion Separate Latch Enable and Output Enable inputs are
provided for each register to permit independent control of
inputting and outputting in either direction of data flow The
A outputs are guaranteed to sink 24 mA (20 mA Mil) while
the B outputs are rated for 64 mA (48 mA Mil) The ’F544
inverts data in both directions
Features
Y
Y
Y
Y
Y
8-bit octal transceiver
Back-to-back registers for storage
Separate controls for data flow in each direction
A outputs sink 24 mA (20 mA Mil) B outputs sink
64 mA (48 mA Mil)
300 mil slim PDIP
Commercial
74F544SPC
Military
Package
Number
N24C
Package Description
24-Lead (0 300 Wide) Molded Dual-In-Line
24-Lead Ceramic Dual-In-Line
24-Lead (0 300 Wide) Ceramic Dual-In-Line
24-Lead (0 300 Wide) Molded Small Outline JEDEC
24-Lead Molded Shrink Small Outline EIAJ Type II
24-Lead Cerpack
24-Lead Ceramic Leadless Chip Carrier Type C
54F544DM (Note 2)
54F544SDM (Note 2)
74F544SC (Note 1)
74F544MSA (Note 1)
54F544FM (Note 2)
54F544LM (Note 2)
J24A
J24F
M24B
MSA24
W24C
E28A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and MSAX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9555 – 2
TL F 9555 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9555
RRD-B30M75 Printed in U S A
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9555 – 4
TL F 9555– 3
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
Input I
IH
I
IL
Output I
OH
I
OL
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A
0
–A
7
B
0
–B
7
A-to-B Output Enable Input (Active LOW)
10 10
20
mA
b
0 6 mA
B-to-A Output Enable Input (Active LOW)
10 10
20
mA
b
0 6 mA
A-to-B Enable Input (Active LOW)
10 20
20
mA
b
1 2 mA
B-to-A Enable Input (Active LOW)
10 20
20
mA
b
1 2 mA
A-to-B Latch Enable Input (Active LOW)
10 10
20
mA
b
0 6 mA
B-to-A Latch Enable Input (Active LOW)
10 10
20
mA
b
0 6 mA
A-to-B Data Inputs or
3 5 1 083
70
mA
b
650
mA
B-to-A TRI-STATE Outputs
150 40(33 3)
b
3 mA 24 mA (20 mA)
B-to-A Data Inputs or
3 5 1 083
70
mA
b
650
mA
b
12 mA 64 mA (48 mA)
A-to-B TRI-STATE Outputs
600 106 6(80)
Functional Description
The ’F544 contains two sets of eight D-type latches with
separate input and output controls for each set For data
flow from A to B for example the A-to-B Enable (CEAB)
input must be LOW in order to enter data from A
0
–A
7
or
take data from B
0
–B
7
as indicated in the Data I O Control
Table With CEAB LOW a LOW signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent
a subsequent LOW-to-HIGH transition of the LEAB signal
puts the A latches in the storage mode and their outputs no
longer change with the A inputs With CEAB and OEAB both
LOW the TRI-STATE B output buffers are active and re-
flect the data present at the output of the A latches Control
of data flow from B to A is similar but using the CEBA
LEBA and OEBA inputs
Data I O Control Table
Inputs
CEAB
H
X
L
X
L
LEAB
X
H
L
X
X
OEAB
X
X
X
H
L
Latched
Latched
Transparent
High Z
Latch Status
Output Buffers
High Z
Driving
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
A-to-B data flow shown B-to-A flow control is the same
except using CEBA LEBA and OEBA
2
Logic Diagram
TL F 9555 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
3
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
b
65 C to
a
150 C
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
b
0 5V to
a
7 0V
b
30 mA to
a
5 0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
b
0 5V to V
CC
Standard Output
b
0 5V to
a
5 5V
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
54F 10% V
CC
54F 10% V
CC
54F 10% V
CC
74F 10% V
CC
74F 10% V
CC
74F 10% V
CC
74F 5% V
CC
74F 5% V
CC
54F 10% V
CC
54F 10% V
CC
74F 10% V
CC
74F 10% V
CC
54F
74F
54F
74F
54F
74F
54F
74F
74F
74F
4 75
3 75
b
0 6
b
1 2
54F 74F
Typ
Max
Units
V
08
b
1 2
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
Min
I
IN
e b
18 mA
(except A
n
B
n
)
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OL
I
OL
I
OL
I
OL
e
e
e
e
e
e
e
e
e
e
e
e
b
1 mA (A
n
)
b
3 mA (A
n
B
n
)
b
12 mA (B
n
)
b
1 mA (A
n
)
b
3 mA (A
n
B
n
)
b
15 mA (B
n
)
b
1 mA (A
n
)
b
3 mA (A
n
B
n
)
25
24
20
25
24
20
27
27
05
0 55
05
0 55
20 0
50
100
70
10
05
250
250
V
Min
V
OL
Output LOW
Voltage
V
Min
20 mA (A
n
)
48 mA (B
n
)
24 mA (A
n
)
64 mA (B
n
)
I
IH
I
BVI
I
BVIT
I
CEX
V
ID
I
OD
I
IL
I
IH
a
I
OZH
I
IL
a
I
OZL
Input HIGH
Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I O)
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
mA
mA
mA
mA
V
mA
mA
mA
mA
Max
Max
Max
Max
00
00
Max
Max
Max
V
IN
e
2 7V (except A
n
B
n
)
V
IN
e
7 0V (except A
n
B
n
)
V
IN
e
5 5V (A
n
B
n
)
V
OUT
e
V
CC
(A
n
B
n
)
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V (OEAB OEBA)
V
IN
e
0 5V (CEAB CEBA)
V
OUT
e
2 7V (A
n
B
n
)
V
OUT
e
0 5V (A
n
B
n
)
Output Leakage Current
Output Leakage Current
70
b
650
4
DC Electrical Characteristics
(Continued)
Symbol
I
OS
I
ZZ
I
CCH
I
CCL
I
CCZ
Parameter
Min
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
70
85
83
b
60
b
100
54F 74F
Typ
Max
b
150
b
225
Units
V
CC
Conditions
V
OUT
e
0V (A
n
)
V
OUT
e
0V (B
n
)
V
OUT
e
5 25V (A
n
B
n
)
V
O
e
HIGH
V
O
e
LOW
V
O
e
HIGH Z
mA
mA
mA
mA
mA
Max
0 0V
Max
Max
Max
500
105
130
125
AC Electrical Characteristics
74F
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
Transparent Mode
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEBA to A
n
Propagation Delay
LEAB to B
n
Output Enable Time
OEBA or OEAB to A
n
or B
n
CEBA or CEAB to A
n
or B
n
Output Disable Time
OEBA or OEAB to A
n
or B
n
CEBA or CEAB to A
n
or B
n
30
30
60
40
60
40
30
40
10
25
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Typ
70
50
10 0
70
10 0
70
70
75
60
55
Max
95
65
13 0
95
13 0
95
90
10 5
80
10 5
54F
T
A
V
CC
e
Mil
C
L
e
50 pF
Min
30
25
60
40
60
40
30
40
20
20
Max
12 0
85
18 0
11 5
18 0
11 5
11 0
13 0
10 0
95
74F
T
A
V
CC
e
Com
C
L
e
50 pF
Min
30
30
60
40
60
40
30
40
10
25
Max
10 5
75
14 5
10 5
14 5
10 5
10 0
12 0
ns
90
11 5
ns
Units
ns
ns
AC Operating Requirements
74F
Symbol
Parameter
T
A
e a
25 C
V
CC
e a
5 0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(L)
Setup Time HIGH or LOW
A
n
or B
n
to LEBA or LEAB
Hold Time HIGH or LOW
A
n
or B
n
to LEBA or LEAB
Latch Enable B to A
Pulse Width LOW
30
30
30
30
60
Max
54F
T
A
V
CC
e
Mil
Min
30
30
30
30
90
Max
74F
T
A
V
CC
e
Com
Min
30
30
30
30
75
ns
Max
Units
ns
5
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