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IDT72T54262L6-7BBG: 产品描述FIFO, 128KX20, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324; 产品类别存储; 文件大小553KB，共56页; 制造商IDT (Integrated Device Technology); 标准

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IDT72T54262L6-7BBG概述

FIFO, 128KX20, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324

IDT72T54262L6-7BBG规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	BGA
包装说明	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
针数	324
Reach Compliance Code	compliant
ECCN代码	EAR99
Is Samacsys	N
最长访问时间	3.8 ns
其他特性	CAN ALSO BE CONFIGURED AS 131,072 X 10 X 4
周期时间	6.7 ns
JESD-30 代码	S-PBGA-B324
JESD-609代码	e1
长度	19 mm
内存密度	2621440 bit
内存宽度	20
湿度敏感等级	3
功能数量	1
端子数量	324
字数	131072 words
字数代码	128000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	128KX20
可输出	YES
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装形状	SQUARE
封装形式	GRID ARRAY
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
认证状态	Not Qualified
座面最大高度	1.97 mm
最大供电电压 (Vsup)	2.625 V
最小供电电压 (Vsup)	2.375 V
标称供电电压 (Vsup)	2.5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	TIN SILVER COPPER
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	30
宽度	19 mm
Base Number Matches	1

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2.5V QUAD/DUAL TeraSync™ DDR/SDR FIFO

x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS

32,768 x 10 x 4/16,384 x 20 x 2

65,536 x 10 x 4/32,768 x 20 x 2

131,072 x 10 x 4/65,536 x 20 x 2

IDT72T54242

IDT72T54252

IDT72T54262

FEATURES

•

Choose from among the following memory organizations:

IDT72T54242 - 32,768 x 10 x 4/32,768 x 10 x 2

IDT72T54252 - 65,536 x 10 x 4/65,536 x 10 x 2

IDT72T54262 - 131,072 x 10 x 4/131,072 x 10 x 2

User Selectable Quad / Dual Mode - Choose between two or

four independent FIFOs

Quad Mode offers

- Eight discrete clock domain, (four write clocks & four read clocks)

- Four separate write ports, write data to four independent FIFOs

- 10-bit wide write ports

- Four separate read ports, read data from any of four independent FIFOs

- Independent set of status flags and control signals for each FIFO

Dual Mode offers

- Four discrete clock domain, (two write clocks & two read clocks)

- Two separate write ports, write data to two independent FIFOs

- 10-bit/20-bit wide write ports

- Two separate read ports, read data from any of two independent FIFOs

- Independent set of status flags and control signals for each FIFO

- Bus-Matching on read and write port x10/x20

- Maximum depth of each FIFO is the same as in Quad Mode

•

Up to 200MHz operating frequency or 2Gbps throughput in SDR mode

Up to 100MHz operating frequency or 2Gbps throughput in DDR mode

Double Data Rate, DDR is selectable, providing up to 400Mbps

bandwidth per data pin

User selectable Single or Double Data Rate modes on both the

write port(s) and read port(s)

All I/Os are LVTTL/ HSTL/ eHSTL user selectable

3.3V tolerant inputs in LVTTL mode

ERCLK and

EREN

Echo outputs on all read ports

Write enable

WEN

and Chip Select

WCS

input for each write port

Read enable

REN

and Chip Select

RCS

input for each read port

User Selectable IDT Standard mode (using

and

FF)

or FWFT

mode (using

and

OR)

Programmable Almost Empty and Almost Full flags per FIFO

Dedicated Serial Port for flag offset programming

Power Down pin minimizes power consumption

2.5V Supply Voltage

Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm

IEEE 1149.1 compliant JTAG port provides boundary scan function

Low Power, High Performance CMOS technology

Industrial temperature range (-40°C to +85°C)

FUNCTIONAL BLOCK DIAGRAMS

Quad Mode

RCLK0

REN0

RCS0

OE0

ERCLK0

EREN0

x10

FIFO 0

Data In

WCLK0

WEN0

WCS0

D[9:0]

x10

32,768 x 10

65,536 x 10

131,072 x 10

Q[9:0]

RCLK1

REN1

RCS1

OE1

ERCLK1

EREN1

FIFO 0

Data Out

FIFO 1

Data In D[19:10]

WCLK1

WEN1

WCS1

x10

32,768 x 10

65,536 x 10

131,072 x 10

FIFO 1

x10

FIFO 1

Q[19:10] Data Out

FIFO 2

Data In D[29:20]

WCLK2

WEN2

WCS2

x10

32,768 x 10

65,536 x 10

131,072 x 10

FIFO 2

RCLK2

REN2

RCS2

OE2

ERCLK2

EREN2

x10

Q[29:20]

RCLK3

REN3

RCS3

OE3

ERCLK3

EREN3

FIFO 2

Data Out

FIFO 3

Data In D[39:30]

WCLK3

WEN3

WCS3

x10

32,768 x 10

65,536 x 10

131,072 x 10

FIFO 3

x10

Q[39:30]

EF0/OR0

PAE0

EF1/OR1

PAE1

EF2/OR2

PAE2

EF3/OR3

PAE3

FIFO 3

Data Out

FF0/IR0

PAF0

FF1/IR1

PAF1

FF2/ IR2

PAF2

FF3/IR3

PAF3

Read Port

Flag Outputs

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The TeraSync is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES



2005

Write Port

Flag Outputs

6158 drw01

(See next page for Dual Mode)

MARCH 2005

DSC-6158/3

IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync

™

DDR/SDR FIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Table of Contents

Features ......................................................................................................................................................................................................................... 1

Description ...................................................................................................................................................................................................................... 4

Pin Configuration ............................................................................................................................................................................................................. 6

Pin Descriptions ............................................................................................................................................................................................................... 7

Device Characteristics ................................................................................................................................................................................................... 11

DC Electrical Characteristics .......................................................................................................................................................................................... 12

AC Electrical Characteristics ........................................................................................................................................................................................... 14

AC Test Conditions ........................................................................................................................................................................................................ 15

Functional Description ................................................................................................................................................................................................... 17

Signal Descriptions ........................................................................................................................................................................................................ 23

JTAG Timing Specifications ............................................................................................................................................................................................ 29

List of Tables

Table 1 — Device Configuration .................................................................................................................................................................................... 17

Table 2 — Default Programmable Flag Offsets ................................................................................................................................................................ 17

Table 3 — Status Flags for IDT Standard mode ............................................................................................................................................................. 20

Table 4 — Status Flags for FWFT mode ........................................................................................................................................................................ 20

Table 5 — I/O Voltage Level Associations ....................................................................................................................................................................... 21

Table 6 — T

SKEW

Measurement ................................................................................................................................................................................... 27

List of Figures

Figure 1. Quad/Dual Block Diagram ................................................................................................................................................................................ 5

Figure 2a. AC Test Load ................................................................................................................................................................................................ 15

Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 15

Figure 3. Programmable Flag Offset Programming Methods ........................................................................................................................................... 18

Figure 4. Offset Registers Serial Bit Sequence ................................................................................................................................................................ 19

Figure 5. Bus-Matching in Dual mode ............................................................................................................................................................................ 22

Figure 6. Echo Read Clock and Data Output Relationship .............................................................................................................................................. 27

Figure 7. Standard JTAG Timing ................................................................................................................................................................................... 28

Figure 8. JTAG Architecture ........................................................................................................................................................................................... 29

Figure 9. TAP Controller State Diagram ......................................................................................................................................................................... 30

Figure 10. Master Reset Timing ..................................................................................................................................................................................... 33

Figure 11. Partial Reset Timing ...................................................................................................................................................................................... 34

Figure 12. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, SDR to SDR) ....................................................................................... 35

Figure 13. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, DDR to DDR) ....................................................................................... 36

Figure 14. Write Cycle and Full Flag Timing (Dual mode, IDT Standard mode, DDR to SDR, x10 In to x20 Out) ............................................................ 37

Figure 15. Write Cycle and Full Flag (Dual mode, IDT Standard mode, SDR to DDR, x20 In to x10 Out) ....................................................................... 38

Figure 16. Write Cycle and Output Ready Timing (Quad mode, FWFT mode, SDR to SDR) .......................................................................................... 39

Figure 17. Write Cycle and Output Ready Timing (Quad mode, FWFT mode, DDR to DDR) .......................................................................................... 40

Figure 18. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, SDR to SDR) ........................................................... 41

Figure 19. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, DDR to DDR) .......................................................... 42

Figure 20. Read Cycle and Empty Flag Timing (Dual mode, IDT Standard mode, DDR to SDR, x20 In to x10 Out) ....................................................... 43

Figure 21. Read Cycle and Empty Flag Timing (Dual mode, IDT Standard mode, SDR to DDR, x10 In to x20 Out) ....................................................... 44

Figure 22. Read Timing and Output Ready Flag (Quad mode, FWFT mode, SDR to SDR) ........................................................................................... 45

Figure 23. Read Timing and Output Ready Timing (Quad mode, FWFT mode, DDR to DDR) ........................................................................................ 46

Figure 24. Read Cycle and Read Chip Select (Quad mode, IDT Standard mode, SDR to SDR) .................................................................................... 47

Figure 25. Read Cycle and Read Chip Select Timing (Quad mode, FWFT mode, SDR to SDR) .................................................................................... 48

Figure 26. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, DDR to DDR) ................................................................. 49

Figure 27. Echo RCLK and Echo Read Enable Operation (Quad mode, FWFT mode, SDR to SDR) ............................................................................. 50

Figure 28. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, SDR to SDR) .................................................................. 51

Figure 29. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 52

Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 52

Figure 32. Synchronous Programmable Almost-Empty Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR) ................................... 53

Figure 31. Synchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR) ....................................... 53

Figure 33. Asynchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR) ...................................... 54

Figure 34. Asynchronous Programmable Almost-Empty Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR) .................................. 54

Figure 35. Power Down Operation ................................................................................................................................................................................ 55

MARCH 22, 2005

IDT72T54262L6-7BBG

IDT72T54262L6-7BBG概述

IDT72T54262L6-7BBG规格参数

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