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74VHCT240ACW

产品描述Bus Driver, AHCT/VHCT Series, 2-Func, 4-Bit, Inverted Output, CMOS
产品类别逻辑   
文件大小85KB,共7页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
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74VHCT240ACW概述

Bus Driver, AHCT/VHCT Series, 2-Func, 4-Bit, Inverted Output, CMOS

74VHCT240ACW规格参数

参数名称属性值
厂商名称Fairchild
包装说明DIE,
Reach Compliance Codeunknown
Is SamacsysN
系列AHCT/VHCT
JESD-30 代码X-XUUC-N20
逻辑集成电路类型BUS DRIVER
位数4
功能数量2
端口数量2
端子数量20
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性INVERTED
封装主体材料UNSPECIFIED
封装代码DIE
封装形状UNSPECIFIED
封装形式UNCASED CHIP
传播延迟(tpd)10 ns
认证状态Not Qualified
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式NO LEAD
端子位置UPPER
Base Number Matches1

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74VHCT240A Octal Buffer/Line Driver with 3-STATE Outputs
March 1997
Revised March 1999
74VHCT240A
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The VHCT240A is an advanced high speed CMOS octal
bus transceiver fabricated with silicon gate CMOS technol-
ogy. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The VHCT240A is an inverting 3-STATE
buffer having two active-LOW output enables. This device
is designed to be used as 3-STATE memory address driv-
ers, clock drivers, and bus oriented transmitter/receivers.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. These circuits prevent device destruction
due to mismatched supply and input/output voltages. This
device can be used to interface 5V to 3V systems and two
supply systems such as battery back up.
Note 1:
Outputs in OFF-State
Features
s
High Speed: t
PD
=
5.6 ns (typ) at V
CC
=
5V
s
Power down protection is provided on inputs and
outputs
s
Low power dissipation: I
CC
=
4
µA
(max) @ T
A
=
25°C
s
Pin and function compatible with 74HCT240
Ordering Code:
Order Number
74VHCT240AM
74VHCT240ASJ
74VHCT240AMTC
74VHCT240AN
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Description
3-STATE Output Enable
Inputs
Outputs 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation
DS500002.prf
www.fairchildsemi.com

 
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