RMPA19000
June 2004
RMPA19000
18–22 GHz Power Amplifier MMIC
General Description
The Fairchild Semiconductor RMPA19000 is a high
efficiency driver amplifier designed for use in point to point
and point to multi-point radios, and various communi-
cations applications. The RMPA19000 is a 3-stage GaAs
MMIC amplifier utilizing our advanced 0.15µm gate length
Power PHEMT process and can be used in conjunction
with other driver or power amplifiers to achieve the required
total power output.
Features
• 28dB small signal gain (typ.)
• 29dBm saturated power out (typ.)
• Circuit contains individual source Vias
• Chip Size 4.45mm x 3.50mm
Device
Absolute Ratings
Symbol
Vd
Vg
Vdg
I
D
P
IN
T
C
T
STG
R
JC
Parameter
Positive DC Voltage (+5V Typical)
Negative DC Voltage
Simultaneous (Vd–Vg)
Positive DC Current
RF Input Power (from 50
Ω
source)
Operating Baseplate Temperature
Storage Temperature Range
Thermal Resistance (Channel to Backside)
Ratings
+6
-2
8
1092
+10
-30 to +85
-55 to +125
16
Units
V
V
V
mA
dBm
°C
°C
°C/W
©2004 Fairchild Semiconductor Corporation
RMPA19000 Rev. C
RMPA19000
Electrical Characteristics
(At 25°C), 50
Ω
system, Vd = +5V, Quiescent current (Idq) = 600mA
Parameter
Frequency Range
Gain Supply Voltage (Vg)
1
Gain Small Signal at Pin = -5dBm
Gain Variation vs. Frequency
Power Output at 1dB Compression
Power Output Saturated: (Pin = +5dBm)
Drain Current at Pin = -5dBm
Drain Current at P1dB Compression
Power Added Efficiency (PAE): at P1dB
OIP3
Input Return Loss (Pin = -5dBm)
Output Return Loss (Pin = -5 dBm)
Note:
1. Typical range of negative gate voltage is -0.9V to 0.0V to set typical Idq of 600mA.
Min
18
22
Typ
-0.2
26
±1
28
29
600
660
15
37
8
10
Max
22
26
Units
GHz
V
dB
dB
dBm
dBm
mA
mA
%
dBm
dB
dB
©2004 Fairchild Semiconductor Corporation
RMPA19000 Rev. C
RMPA19000
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE.
Chip carrier material should be selected to have GaAs compatible thermal coefficient of expansion and high thermal
conductivity such as copper molybdenum or copper tungsten. The chip carrier should be machined, finished flat, plated with
gold over nickel and should be capable of withstanding 325°C for 15 minutes.
Die attachment should utilize Gold/Tin (80/20) eutectic alloy solder and should avoid hydrogen environment for PHEMT
devices. Note that the backside of the chip is gold plated and is used as RF and DC ground.
These GaAs devices should be handled with care and stored in dry nitrogen environment to prevent contamination of
bonding surfaces. These are ESD sensitive devices and should be handled with appropriate precaution including the use of
wrist grounding straps. All die attach and wire/ribbon bond equipment must be well grounded to prevent static discharges
through the device.
Recommended wire bonding uses 3 mils wide and 0.5 mil thick gold ribbon with lengths as short as practical allowing for
appropriate stress relief. The RF input and output bonds should be typically 0.012" long corresponding to a typical 2 mil gap
between the chip and the substrate material.
DRAIN SUPPLY
(VDA & VDB)
MMIC CHIP
RF IN
RF OUT
GROUND
(Back of the Chip)
GATE SUPPLY
(VGA & VGB)
Figure 1. Functional Block Diagram
3.500
3.324
3.126
1.930
1.750
1.570
0.378
0.0
0.0
0.152
3.910
4.450
0.181
0.0
Dimensions in mm
Figure 2. Chip Layout and Bond Pad Locations
(Chip Size is 4.450mm x 3.500mm x 50µm. Back of chip is RF and DC Ground)
©2004 Fairchild Semiconductor Corporation
RMPA19000 Rev. C
RMPA19000
DRAIN SUPPLY (Vd = +5V)
(Connect to both VDA & VDB)
10000pF
L
BOND WIRE Ls
10 0pF
L
MMIC CHIP
RF IN
RF OUT
L
GROUND
(Back of Chip)
BOND WIRE Ls
100pF
L
10000pF
GATE SUPPLY (Vg)
(VGA and/or VGB)
Figure 3. Recommended Application Schematic Circuit Diagram
©2004 Fairchild Semiconductor Corporation
RMPA19000 Rev. C
RMPA19000
Vg (NEGATIVE)
Vd (POSITIVE)
DIE-ATTACH
80Au/20Sn
10000pF
2 MIL GAP
10000pF
100pF
100pF
5 MIL THICK
ALUMINA
50Ω
5 MIL THICK
ALUMINA
50Ω
RF INPUT
RF OUTPUT
100pF
100pF
10000pF
10000pF
L < 0.015"
(4 Places)
Vg (NEGATIVE)
Vd (POSITIVE)
Note:
Use 0.003" by 0.0005" Gold Ribbon for bonding. RF input and output bonds should be less than 0.015" long with stress relief.
Vd should be biased from 1 supply as shown. Vg can be biased from either or both sides from 1 supply.
Figure 4. Recommended Assembly and Bonding Diagram
©2004 Fairchild Semiconductor Corporation
RMPA19000 Rev. C
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