SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003
D
Package Options Include Plastic
Small-Outline (D, NS, PS), Shrink
Small-Outline (DB), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J) DIPs
SN5400 . . . J PACKAGE
SN54LS00, SN54S00 . . . J OR W PACKAGE
SN7400, SN74S00 . . . D, N, OR NS PACKAGE
SN74LS00 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
D
Also Available as Dual 2-Input
Positive-NAND Gate in Small-Outline (PS)
Package
SN74LS00, SN74S00 . . . PS PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
1A
1B
1Y
GND
1
2
3
4
8
7
6
5
V
CC
2B
2A
2Y
SN5400 . . . W PACKAGE
(TOP VIEW)
SN54LS00, SN54S00 . . . FK PACKAGE
(TOP VIEW)
1A
1B
1Y
V
CC
2Y
2A
2B
1
2
3
4
5
6
7
14
13
12
11
10
9
8
4Y
4B
4A
GND
3B
3A
3Y
1B
1A
NC
V
CC
4B
1Y
NC
2A
NC
2B
3
4
5
6
7
8
2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3B
NC − No internal connection
description/ordering information
These devices contain four independent 2-input NAND gates. The devices perform the Boolean function
Y = A
•
B or Y = A + B in positive logic.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2Y
GND
NC
3Y
3A
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
1
SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
description/ordering information (continued)
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
SN7400N
PDIP − N
Tube
Tube
Tape and reel
Tube
SOIC − D
0 C 70 C
0°C to 70°C
Tape and reel
Tube
Tape and reel
SN74LS00N
SN74S00N
SN7400D
SN7400DR
SN74LS00D
SN74LS00DR
SN74S00D
SN74S00DR
SN7400NSR
SOP − NS
Tape and reel
SN74LS00NSR
SN74S00NSR
SN74LS00PSR
SOP − PS
SSOP − DB
Tape and reel
Tape and reel
SN74S00PSR
SN74LS00DBR
SNJ5400J
CDIP − J
Tube
SNJ54LS00J
SNJ54S00J
SNJ5400W
−55°C to 125°C
CFP − W
Tube
SNJ54LS00W
SNJ54S00W
SNJ54LS00FK
LCCC − FK
Tube
SNJ54S00FK
S00
SN7400
74LS00
74S00
LS00
S00
LS00
SNJ5400J
SNJ54LS00J
SNJ54S00J
SNJ5400W
SNJ54LS00W
SNJ54S00W
SNJ54LS00FK
SNJ54S00FK
LS00
7400
TOP-SIDE
MARKING
SN7400N
SN74LS00N
SN74S00N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
logic diagram, each gate (positive logic)
A
B
Y
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003
schematic
’00
VCC
4 kΩ
1.6 kΩ
130
Ω
A
B
Y
1 kΩ
GND
’LS00
VCC
20 kΩ
8 kΩ
120
Ω
2.8 kΩ
’S00
VCC
900
Ω
50
Ω
A
3.5 kΩ
B
12 kΩ
4 kΩ
Y
A
B
Y
500
Ω
250
Ω
1.5 kΩ
3 kΩ
GND
GND
Resistor values shown are nominal.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage, V
CC
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage: ’00, ’S00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
’LS00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN5400
MIN
VCC
VIH
VIL
IOH
IOL
TA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
−55
4.5
2
0.8
−0.4
16
125
0
NOM
5
MAX
5.5
MIN
4.75
2
0.8
−0.4
16
70
SN7400
NOM
5
MAX
5.25
UNIT
V
V
V
mA
mA
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
IIL
IOS¶
ICCH
ICCL
VCC = MIN,
VCC = MIN,
VCC = MIN,
VCC = MAX,
VCC = MAX,
VCC = MAX,
VCC = MAX
VCC = MAX,
VCC = MAX,
VI = 0 V
VI = 4.5 V
TEST CONDITIONS‡
II = −12 mA
VIL = 0.8 V,
VIH = 2 V,
VI = 5.5 V
VI = 2.4 V
VI = 0.4 V
−20
4
12
SN5400
MIN
TYP§
MAX
−1.5
IOH = −0.4 mA
IOL = 16 mA
2.4
3.4
0.2
0.4
1
40
−1.6
−55
8
22
−18
4
12
2.4
3.4
0.2
0.4
1
40
−1.6
−55
8
22
MIN
SN7400
TYP§
MAX
−1.5
UNIT
V
V
V
mA
µA
mA
mA
mA
mA
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at VCC = 5 V, TA = 25°C.
¶ Not more than one output should be shorted at a time.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN5400, SN54LS00, SN54S00
SN7400, SN74LS00, SN74S00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003
switching characteristics, V
CC
= 5 V, T
A
= 25°C (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
RL = 400
Ω,
CL = 15 pF
SN5400
SN7400
TYP
11
7
MAX
22
15
ns
UNIT
A or B
Y
recommended operating conditions (see Note 4)
SN54LS00
MIN
VCC
VIH
VIL
IOH
IOL
TA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
−55
4.5
2
0.7
−0.4
4
125
0
NOM
5
MAX
5.5
SN74LS00
MIN
4.75
2
0.8
−0.4
8
70
NOM
5
MAX
5.25
UNIT
V
V
V
mA
mA
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
IIL
IOS§
ICCH
ICCL
VCC = MIN,
VCC = MIN,
VCC = MIN,
VCC = MAX,
VCC = MAX,
VCC = MAX,
VCC = MAX
VCC = MAX,
VCC = MAX,
VI = 0 V
VI = 4.5 V
TEST CONDITIONS†
II = −18 mA
VIL = MAX,
VIH = 2 V
VI = 7 V
VI = 2.7V
VI = 0.4 V
−20
0.8
2.4
SN54LS00
MIN
TYP‡
MAX
−1.5
IOH = −0.4 mA
IOL = 4 mA
IOL = 8mA
0.1
20
−0.4
−100
1.6
4.4
−20
0.8
2.4
2.5
3.4
0.25
0.4
2.7
3.4
0.25
0.35
0.4
0.5
0.1
20
−0.4
−100
1.6
4.4
V
mA
µA
mA
mA
mA
mA
SN74LS00
MIN
TYP‡
MAX
−1.5
UNIT
V
V
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time.
switching characteristics, V
CC
= 5 V, T
A
= 25°C (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN54LS00
SN74LS00
MIN
RL = 2 kΩ,
CL = 15 pF
TYP
9
10
MAX
15
15
ns
UNIT
A or B
Y
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
stm32/stm8
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