functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50Ω while delivering minimal and specified output skews
and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to
±6
time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to
±12
time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
•
•
•
•
•
•
•
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
Zero input to output delay
50% duty-cycle outputs
Outputs drive 50Ω terminated lines
Low operating current
32-pin PLCC/LCC package
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Compatible with a Pentium™-based processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buff-
ers (PSCB) offer user-selectable control over system clock
Logic Block Diagram
TEST
Pin Configuration
PLCC/LCC
3F0
2F1
FS
FILTER
REF
FS
4F0
4F1
4
3F1
4Q0
SELECT
INPUTS
(THREE
LEVEL)
4Q1
V
CCQ
SKEW
3Q0
3Q1
SELECT
2Q0
MATRIX
2Q1
1Q0
1Q1
7B991–1
3
2
1
5
6
7
8
9
10
11
12
32 31 30
29
28
27
26
TEST
V
CCQ
GND
REF
FB
PHASE
FREQ
DET
VCO AND
TIME UNIT
GENERATOR
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
4F0
4F1
3F0
3F1
V
CCN
4Q1
4Q0
GND
GND
CY7B991
CY7B992
25
24
23
22
2F0
2F1
13
21
14 15 16 17 18 19 20
3Q1
3Q0
FB
2Q1
V
CCN
V
CCN
2Q0
1F0
1F1
7B991–2
Pentium is a trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07138 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 26, 2001
CY7B991
CY7B992
Pin Definitions
Signal
Name
REF
FB
FS
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
V
CCN
V
CCQ
GND
I/O
I
I
I
I
I
I
I
I
O
O
O
O
PWR
PWR
PWR
Description
Reference frequency input. This input supplies the frequency and timing against which all functional
variation is measured.
PLL feedback input (typically connected to one of the eight outputs).
Three-level frequency range select. See
Table 1.
Three-level function select inputs for output pair 1 (1Q0, 1Q1). See
Table 2.
Three-level function select inputs for output pair 2 (2Q0, 2Q1). See
Table 2.
Three-level function select inputs for output pair 3 (3Q0, 3Q1). See
Table 2.
Three-level function select inputs for output pair 4 (4Q0, 4Q1). See
Table 2.
Three-level select. See test mode section under the block diagram descriptions.
Output pair 1. See
Table 2.
Output pair 2. See
Table 2.
Output pair 3. See
Table 2.
Output pair 4. See
Table 2.
Power supply for output drivers.
Power supply for internal circuitry.
Ground.
(xF0, xF1) inputs.
Table 2
below shows the nine possible out-
put functions for each section as determined by the function
select inputs. All times are measured with respect to the REF
input assuming that the output connected to the FB input has
0t
U
selected.
Table 2. Programmable Skew Configurations
[1]
Function Selects
1F1, 2F1,
3F1, 4F1
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
Approximate
Frequency (MHz) At
Which t
U
= 1.0 ns
22.7
38.5
62.5
HIGH
1F0, 2F0,
3F0, 4F0
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
Output Functions
1Q0, 1Q1,
2Q0, 2Q1
–4t
U
–3t
U
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
3Q0, 3Q1
–6t
U
–4t
U
–2t
U
0t
U
+2t
U
+4t
U
+6t
U
Divide by 4
4Q0, 4Q1
–6t
U
–4t
U
–2t
U
0t
U
+2t
U
+4t
U
+6t
U
Inverted
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept inputs from the reference frequency
(REF) input and the feedback (FB) input and generate correc-
tion information to control the frequency of the Voltage-Con-
trolled Oscillator (VCO). These blocks, along with the VCO,
form a Phase-Locked Loop (PLL) that tracks the incoming
REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter
block and generates a frequency that is used by the time unit
generator to create discrete time units that are selected in the
skew select matrix. The operational range of the VCO is de-
termined by the FS control pin. The time unit (t
U
) is determined
by the operating frequency of the device and the level of the
FS pin as shown in
Table 1.
Table 1. Frequency Range Select and t
U
Calculation
[1]
f
NOM
(MHz)
FS
[2, 3]
Min. Max.
LOW
MID
HIGH
15
25
40
30
50
80
1
t
U
=
-----------------------
-
f
NOM
×
N
Divide by 2 Divide by 2
where N =
44
26
16
Skew Select Matrix
The skew select matrix is comprised of four independent sec-
tions. Each section has two low-skew, high-fanout drivers
(xQ0, xQ1), and two corresponding three-level function select
Notes:
1. For all three-state inputs, HIGH indicates a connection to V
CC
, LOW
indicates a connection to GND, and MID indicates an open connection.
Internal termination circuitry holds an unconnected input to V
CC
/2.
2. The level to be set on FS is determined by the “normal” operating fre-
quency (f
NOM
) of the V
CO
and Time Unit Generator (see Logic Block
Diagram). Nominal frequency (f
NOM
) always appears at 1Q0 and the
other outputs when they are operated in their undivided modes (see
Table 2).
The frequency appearing at the REF and FB inputs will be f
NOM
when the output connected to FB is undivided. The frequency of the REF
and FB inputs will be f
NOM
/2 or f
NOM
/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition
upon power-up until V
CC
has reached 4.3V.
Document #: 38-07138 Rev. **
Page 2 of 15
CY7B991
CY7B992
t
0
– 6t
U
t
0
– 5t
U
t
0
– 4t
U
t
0
– 3t
U
t
0
– 2t
U
t
0
– 1t
U
U
U
U
U
U
t
0
+1t
t
0
+2t
t
0
+3t
t
0
+4t
t
0
+5t
FBInput
REFInput
1Fx
2Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
3Fx
4Fx
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
HH
– 6t
U
– 4t
U
– 3t
U
– 2t
U
– 1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
DIVIDED
INVERT
7B991–3
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
[4]
Test Mode
The TEST input is a three-level input. In normal system oper-
ation, this pin is connected to ground, allowing the
CY7B991/CY7B992 to operate as explained briefly above (for
testing purposes, any of the three-level inputs can have a re-
movable jumper to ground, or be tied LOW through a 100Ω
resistor. This will allow an external tester to change the state
of these pins.)
If the TEST input is forced to its MID or HIGH state, the device
will operate with its internal phase locked loop disconnected,
and input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal
mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics
of the REF input.
Ambient Temperature with
Power Applied ............................................ –55
°
C to +125
°
C
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 64 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Military
[5]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Document #: 38-07138 Rev. **
Notes:
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 =
MID).
5. Indicates case temperature.
t
0
+6t
t
0
U
Page 3 of 15
CY7B991
CY7B992
Electrical Characteristics
Over the Operating Range
[6]
CY7B991
Parameter
V
OH
V
OL
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IH
I
IL
I
IHH
I
IMM
I
ILL
I
OS
I
CCQ
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(REF and FB inputs only)
Input LOW Voltage
(REF and FB inputs only)
Three-Level Input HIGH
Voltage (Test, FS, xFn)
[7]
Three-Level Input MID
Voltage (Test, FS, xFn)
[7]
Three-Level Input LOW
Voltage (Test, FS, xFn)
[7]
Input HIGH Leakage Current
(REF and FB inputs only)
Input LOW Leakage Current
(REF and FB inputs only)
Input HIGH Current
(Test, FS, xFn)
Input MID Current
(Test, FS, xFn)
Input LOW Current
(Test, FS, xFn)
Output Short Circuit
Current
[8]
Operating Current Used by
Internal Circuitry
Output Buffer Current per
Output Pair
[9]
Power Dissipation per
Output Pair
[10]
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
V
CC
= Max., V
IN
= Max.
V
CC
= Max., V
IN
= 0.4V
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
= GND
V
CC
= Max., V
OUT
= GND (25
°
C only)
V
CCN
= V
CCQ
=
Max., All Input
Selects Open
Com’l
Mil/Ind
–50
–500
200
50
–200
–250
85
90
14
–50
Test Conditions
V
CC
= Min., I
OH
= –16 mA
V
CC
= Min., I
OH
=–40 mA
V
CC
= Min., I
OL
= 46 mA
V
CC
= Min., I
OL
= 46 mA
2.0
–0.5
V
CC
– 0.85
V
CC
/2 –
500 mV
0.0
V
CC
0.8
V
CC
V
CC
/2 +
500 mV
0.85
10
–500
200
50
–200
N/A
85
90
19
mA
V
CC
–
1.35
–0.5
V
CC
– 0.85
V
CC
/2 –
500 mV
0.0
0.45
0.45
V
CC
1.35
V
CC
V
CC
/2 +
500 mV
0.85
10
V
V
V
V
V
µA
µA
µA
µA
µA
mA
mA
Min.
2.4
V
CC
–0.75
V
Max.
CY7B992
Min.
Max.
Unit
V
I
CCN
V
CCN
= V
CCQ
= Max.,
I
OUT
= 0 mA
Input Selects Open, f
MAX
V
CCN
= V
CCQ
= Max.,
I
OUT
= 0 mA
Input Selects Open, f
MAX
PD
78
104
[11]
mW
Notes:
6. See the last page of this specification for Group A subgroup testing information.
7. These inputs are normally wired to V
CC
, GND, or left unconnected (actual threshold voltages vary as a percentage of V
CC
). Internal termination resistors hold
unconnected inputs at V
CC
/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t
LOCK
time
before all datasheet limits are achieved.
8. CY7B991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs
should not be shorted to GND. Doing so may cause permanent damage.
9. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to
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