74VHC273 Octal D-Type Flip-Flop
April 1994
Revised April 2005
74VHC273
Octal D-Type Flip-Flop
General Description
The VHC273 is an advanced high speed CMOS Octal
D-type flip-flop fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The register has a common buffered Clock (CP) which is
fully edge-triggered. The state of each D input, one setup
time before the LOW-to-HIGH clock transition, is trans-
ferred to the corresponding flip-flop’s Q output. The Master
Reset (MR) input will clear all flip-flops simultaneously. All
outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input.
An input protection circuit insures that 0V to 7V can be
applied to the inputs pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: f
MAX
165 MHz (typ) at V
CC
V
NIL
5V
25
q
C
s
Low power dissipation: I
CC
s
High noise immunity: V
NIH
s
Low noise: V
OLP
4
P
A (max) at T
A
28% V
CC
(min)
s
Power down protection is provided on all inputs
0.9V (max)
s
Pin and function compatible with 74HC273
s
Leadless DQFN Package
Ordering Code:
Order Number
74VHC273M
74VHC273SJ
74VHC273BQ
(Preliminary)
74VHC273MTC
74VHC273N
Package
Number
M20B
M20D
MLP020B
(Preliminary)
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 4.5mm
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
© 2005 Fairchild Semiconductor Corporation
DS011670
www.fairchildsemi.com
74VHC273
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Input Diode Current (I
IK
)
Output Diode Current (I
OK
)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
q
C
0.5V to
7.0V
0.5V to
7.0V
0.5V to V
CC
0.5V
20 mA
r
20 mA
r
25 mA
r
75 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
V
CC
3.3V
r
0.3V
5.0V
r
0.5V
0 ns/V
a
100 ns/V
0 ns/V
a
20 ns/V
2.0V to
5.5V
0V to
5.5V
0V to V
CC
40
q
C to
85
q
C
Note 1:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input
Voltage
LOW Level Input
Voltage
HIGH Level Output
Voltage
V
CC
(V)
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
4.5
V
OL
LOW Level Output
Voltage
2.0
3.0
4.5
3.0
4.5
I
IN
I
CC
Input Leakage Current
Quiescent Supply Current
0
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
2.0
3.0
4.5
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
V
I
OL
I
OL
V
IN
V
IN
5.5V or GND
V
CC
or GND
4 mA
8 mA
V
V
V
IN
I
OH
I
OH
V
IH
I
OL
or V
IL
V
T
A
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Min
1.50
0.7 V
CC
Units
V
Conditions
0.50
0.3 V
CC
V
V
IN
V
IH
I
OH
or V
IL
50
P
A
4 mA
8 mA
50
P
A
r
0.1
4.0
r
1.0
40.0
P
A
P
A
Noise Characteristics
Symbol
V
OLP
(Note 3)
V
OLV
(Note 3)
V
IHD
(Note 3)
V
ILD
(Note 3)
Note 3:
Parameter guaranteed by design.
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
Typ
0.6
T
A
25
q
C
Limits
0.9
Units
V
V
V
V
C
L
C
L
C
L
C
L
Conditions
50 pF
50 pF
50 pF
50 pF
0.6
0.9
3.5
1.5
3
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74VHC273
AC Electrical Characteristics
Symbol
f
MAX
Parameter
Maximum Clock
Frequency
5.0
r
0.5
t
PLH
t
PHL
Propagation Delay
Time (CK - Q)
5.0
r
0.5
t
PHL
Propagation Delay
Time (MR - Q)
5.0
r
0.5
t
OSLH
t
OSHL
C
IN
C
PD
Output to
Output Skew
Input Capacitance
Power Dissipation
Capacitance
Note 4:
Parameter guaranteed by design t
OSLH
|t
PLH
max
t
PLH
min|; t
OSHL
|t
PHL
max
t
PHL
min|.
V
CC
(V)
3.3
r
0.3
Min
75
50
120
80
3.3
r
0.3
T
A
25
q
C
Typ
120
75
165
110
8.7
11.2
5.8
7.3
8.9
11.4
5.2
6.7
13.6
17.1
9.0
11.0
13.6
17.1
8.5
10.5
1.5
1.0
4.0
31
10.0
Max
T
A
40
q
C to
85
q
C
Max
65
45
Min
Units
MHz
MHz
Conditions
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
(Note 4)
V
CC
Open
C
L
C
L
(Note 5)
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
50 pF
50 pF
100
70
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
16.0
19.5
10.5
12.5
16.0
19.5
10.0
12.0
1.5
1.0
10.0
ns
ns
ns
ns
ns
pF
pF
3.3
r
0.3
3.3
r
0.3
5.0
r
0.5
Note 5:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: I
CC
(opr.) C
PD
* V
CC
* f
IN
I
CC
/8 (per F/F). The total C
PD
when n pieces of the Flip-Flop operates can
be calculated by the equation: C
PD
(total) 22
9n.
AC Operating Requirements
Symbol
t
W
(L)
t
W
(H)
t
W
(L)
t
S
t
H
Minimum Pulse Width (MR)
Minimum Setup Time
Minimum Hold Time
Parameter
Minimum Pulse Width (CK)
V
CC
(V)
(Note 6)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
t
REC
Minimum Removal Time (MR)
3.3
5.0
Note 6:
V
CC
is 3.3
r
0.3V or 5.0
r
0.5V
T
A
Typ
25
q
C
T
A
40
q
C to
85
q
C
Units
Guaranteed Minimum
5.5
5.0
5.0
5.0
5.5
4.5
1.0
1.0
2.5
2.0
6.5
5.0
6.0
5.0
6.5
4.5
1.0
1.0
2.5
2.0
ns
ns
ns
ns
ns
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4
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