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IDT6116SA20TD

产品描述Standard SRAM, 2KX8, 19ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
产品类别存储   
文件大小91KB,共10页
制造商IDT (Integrated Device Technology)
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IDT6116SA20TD概述

Standard SRAM, 2KX8, 19ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24

IDT6116SA20TD规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码DIP
包装说明0.300 INCH, CERDIP-24
针数24
Reach Compliance Codenot_compliant
ECCN代码EAR99
Is SamacsysN
最长访问时间19 ns
I/O 类型COMMON
JESD-30 代码R-GDIP-T24
JESD-609代码e0
长度32.004 mm
内存密度16384 bit
内存集成电路类型STANDARD SRAM
内存宽度8
功能数量1
端口数量1
端子数量24
字数2048 words
字数代码2000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织2KX8
输出特性3-STATE
可输出YES
封装主体材料CERAMIC, GLASS-SEALED
封装代码DIP
封装等效代码DIP24,.3
封装形状RECTANGULAR
封装形式IN-LINE
并行/串行PARALLEL
峰值回流温度(摄氏度)225
电源5 V
认证状态Not Qualified
座面最大高度5.08 mm
最大待机电流0.002 A
最小待机电流4.5 V
最大压摆率0.13 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间20
宽度7.62 mm
Base Number Matches1

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CMOS STATIC RAM
16K (2K x 8 BIT)
Integrated Device Technology, Inc.
IDT6116SA
IDT6116LA
FEATURES:
• High-speed access and chip select times
— Military: 20/25/35/45/55/70/90/120/150ns (max.)
— Commercial: 15/20/25/35/45ns (max.)
• Low-power consumption
• Battery backup operation
— 2V data retention voltage (LA version only)
• Produced with advanced CMOS high-performance
technology
• CMOS process virtually eliminates alpha particle
soft-error rates
• Input and output directly TTL-compatible
• Static operation: no clocks or refresh required
• Available in ceramic and plastic 24-pin DIP, 24-pin Thin
Dip and 24-pin SOIC and 24-pin SOJ
• Military product compliant to MIL-STD-833, Class B
DESCRIPTION:
The IDT6116SA/LA is a 16,384-bit high-speed static RAM
organized as 2K x 8. It is fabricated using IDT's high-perfor-
mance, high-reliability CMOS technology.
Access times as fast as 15ns are available. The circuit also
offers a reduced power standby mode. When
CS
goes HIGH,
the circuit will automatically go to, and remain in, a standby
power mode, as long as
CS
remains HIGH. This capability
provides significant system level power and cooling savings.
The low-power (LA) version also offers a battery backup data
retention capability where the circuit typically consumes only
1µW to 4µW operating off a 2V battery.
All inputs and outputs of the IDT6116SA/LA are TTL-
compatible. Fully static asynchronous circuitry is used, requir-
ing no clocks or refreshing for operation.
The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil
plastic or ceramic DIP and a 24-lead gull-wing SOIC, and a 24
-lead J-bend SOJ providing high board-level packing densi-
ties.
Military grade product is manufactured in compliance to the
latest version of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
0
V
CC
ADDRESS
DECODER
A
10
128 X 128
MEMORY
ARRAY
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
CS
OE
WE
CONTROL
CIRCUIT
3089 drw 01
The IDT logo is aregistered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MARCH 1996
3089/1
5.1
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