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Intel 845 Chipset: 82845
Memory Controller Hub (MCH)
Datasheet
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September 2001
Document Number:
290725-001
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
845 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Implementations of the I
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C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
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Copyright © 2001, Intel Corporation
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Intel 82845 MCH Datasheet
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Contents
1
Introduction ........................................................................................................................11
1.1
1.2
1.3
1.4
Terminology and Notations ...................................................................................11
Reference Documents ..........................................................................................13
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Intel 845 Chipset System Architecture ................................................................14
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Intel 82845 MCH Overview .................................................................................14
1.4.1
System Bus Interface ............................................................................15
1.4.2
System Bus Error Checking ..................................................................15
1.4.3
System Memory Interface .....................................................................16
1.4.4
AGP Interface........................................................................................16
1.4.5
Hub Interface.........................................................................................17
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1.4.6
Intel MCH Clocking ..............................................................................17
1.4.7
System Interrupts ..................................................................................18
1.4.8
Powerdown Flow ...................................................................................18
System Bus Signals ..............................................................................................21
SDR SDRAM Interface Signals.............................................................................23
Hub Interface Signals............................................................................................23
AGP Interface Signals...........................................................................................24
2.4.1
AGP Addressing Signals .......................................................................24
2.4.2
AGP Flow Control Signals .....................................................................25
2.4.3
AGP Status Signals ...............................................................................25
2.4.4
AGP Strobes Signals.............................................................................26
2.4.5
AGP/PCI Signals ...................................................................................26
Clocks, Reset, and Miscellaneous Signals ...........................................................28
Voltage Reference and Power Signals .................................................................29
Reset States During Reset ...................................................................................30
2
Signal Description..............................................................................................................19
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3
Register Description ..........................................................................................................31
3.1
3.2
Register Terminology............................................................................................31
PCI Bus Configuration Space Access...................................................................32
3.2.1
Standard PCI Bus Configuration Mechanism........................................33
3.2.2
Routing Configuration Accesses ...........................................................33
I/O Mapped Registers ...........................................................................................34
3.3.1
CONF_ADDR—Configuration Address Register ..................................34
3.3.2
CONF_DATA—Configuration Data Register.........................................36
Memory-Mapped Register Space .........................................................................36
3.4.1
DRAMWIDTH—DRAM Width Register.................................................37
3.4.2
DQCMDSTR—Strength Control Register (SDQ and
CMD Signal Groups) .............................................................................38
3.4.3
CKESTR—Strength Control Register (SCKE Signal Group) ................39
3.4.4
CSBSTR—Strength Control Register (SCS# Signal Group).................40
3.4.5
CKSTR—Strength Control Register (Clock Signal Group) ...................41
3.4.6
RCVENSTR—Strength Control Register (RCVENOUT
Signal Group) ........................................................................................42
3.3
3.4
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3.5
3.6
Host-Hub Interface Bridge Device Registers (Device 0)......................................43
3.5.1
VID—Vendor Identification Register (Device 0) ....................................45
3.5.2
DID—Device Identification Register (Device 0).....................................45
3.5.3
PCICMD—PCI Command Register (Device 0) .....................................46
3.5.4
PCISTS—PCI Status Register (Device 0).............................................47
3.5.5
RID—Revision Identification Register (Device 0)..................................48
3.5.6
SUBC—Sub-Class Code Register (Device 0).......................................48
3.5.7
BCC—Base Class Code Register (Device 0)........................................48
3.5.8
MLT—Master Latency Timer Register (Device 0) .................................49
3.5.9
HDR—Header Type Register (Device 0) ..............................................49
3.5.10 APBASE—Aperture Base Configuration Register (Device 0) ...............50
3.5.11 SVID—Subsystem Vendor Identification (Device 0) .............................51
3.5.12 SID—Subsystem Identification (Device 0) ............................................51
3.5.13 CAPPTR—Capabilities Pointer (Device 0) ............................................51
3.5.14 DWTC—DRAM Write Thermal Management Control
Register (Device 0)................................................................................52
3.5.15 AGPM—AGP Miscellaneous Configuration Register (Device 0)...........53
3.5.16 DRTC—DRAM Read Thermal Management Control
Register (Device 0)................................................................................54
3.5.17 DRB[0:7]—DRAM Row Boundary Registers (Device 0)........................55
3.5.18 DRA—DRAM Row Attribute Registers (Device 0) ................................56
3.5.19 DRT—DRAM Timing Register (Device 0) .............................................58
3.5.20 DRC—DRAM Controller Mode Register (Device 0) ..............................59
3.5.21 DERRSYN—DRAM Error Syndrome Register (Device 0) ....................61
3.5.22 EAP—Error Address Pointer Register (Device 0) .................................61
3.5.23 PAM[0:6]—Programmable Attribute Map Registers (Device 0) ...........62
3.5.24 FDHC—Fixed DRAM Hole Control Register (Device 0)........................65
3.5.25 SMRAM—System Management RAM Control Register (Device 0) ......66
3.5.26 ESMRAMC—Extended System Mgmt RAM Control
Register (Device 0)................................................................................67
3.5.27 ACAPID—AGP Capability Identifier Register (Device 0).......................68
3.5.28 AGPSTAT—AGP Status Register (Device 0) .......................................69
3.5.29 AGPCMD—AGP Command Register (Device 0)..................................70
3.5.30 AGPCTRL—AGP Control Register (Device 0)......................................71
3.5.31 APSIZE—Aperture Size (Device 0) .......................................................72
3.5.32 ATTBASE—Aperture Translation Table Base Register (Device 0).......73
3.5.33 AMTT—AGP Interface Multi-Transaction Timer Register (Device 0) ...74
3.5.34 LPTT—AGP Low Priority Transaction Timer Register (Device 0).........75
3.5.35 TOM—Top of Low Memory Register (Device 0) ...................................76
3.5.36 MCHCFG—MCH Configuration Register (Device 0).............................77
3.5.37 ERRSTS—Error Status Register (Device 0) .........................................78
3.5.38 ERRCMD—Error Command Register (Device 0) .................................79
3.5.39 SMICMD—SMI Command Register (Device 0) ....................................81
3.5.40 SCICMD—SCI Command Register (Device 0) .....................................81
3.5.41 SKPD—Scratchpad Data Register (Device 0) ......................................82
3.5.42 CAPID—Product Specific Capability Identifier Register (Device 0) ......82
Bridge Registers (Device 1) ..................................................................................83
3.6.1
VID1—Vendor Identification Register (Device 1) ..................................84
3.6.2
DID1—Device Identification Register (Device 1)...................................84
3.6.3
PCICMD1—PCI-PCI Command Register (Device 1)............................85
3.6.4
PCISTS1—PCI-PCI Status Register (Device 1)....................................86
3.6.5
RID1—Revision Identification Register (Device 1)................................87
3.6.6
SUBC1—Sub-Class Code Register (Device 1).....................................87
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Intel 82845 MCH Datasheet
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3.6.7
3.6.8
3.6.9
3.6.10
3.6.11
3.6.12
3.6.13
3.6.14
3.6.15
3.6.16
3.6.17
3.6.18
3.6.19
3.6.20
3.6.21
3.6.22
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4.1
BCC1—Base Class Code Register (Device 1)......................................87
MLT1—Master Latency Timer Register (Device 1) ...............................88
HDR1—Header Type Register (Device 1) ............................................88
PBUSN1—Primary Bus Number Register (Device 1) ...........................88
SBUSN1—Secondary Bus Number Register (Device 1) ......................89
SUBUSN1—Subordinate Bus Number Register (Device 1)..................89
SMLT1—Secondary Master Latency Timer Register (Device 1) .........90
IOBASE1—I/O Base Address Register (Device 1) ...............................91
IOLIMIT1—I/O Limit Address Register (Device 1) ................................91
SSTS1—Secondary PCI-PCI Status Register (Device 1) .....................92
MBASE1—Memory Base Address Register (Device 1) ........................93
MLIMIT1—Memory Limit Address Register (Device 1) .........................93
PMBASE1—Prefetchable Memory Base Address
Register (Device 1)................................................................................94
PMLIMIT1—Prefetchable Memory Limit Address
Register (Device 1)................................................................................95
BCTRL1—PCI-PCI Bridge Control Register (Device 1) ........................96
ERRCMD1—Error Command Register (Device 1) ...............................97
System Address Map.........................................................................................................99
Memory Address Ranges .....................................................................................99
4.1.1
VGA and MDA Memory Space............................................................101
4.1.2
PAM Memory Spaces..........................................................................102
4.1.3
ISA Hole Memory Space .....................................................................102
4.1.4
TSEG SMM Memory Space ................................................................103
4.1.5
IOAPIC Memory Space .......................................................................103
4.1.6
System Bus Interrupt APIC Memory Space ........................................103
4.1.7
High SMM Memory Space...................................................................103
4.1.8
AGP Aperture Space (Device 0 BAR) .................................................104
4.1.9
AGP Memory and Prefetchable Memory.............................................104
4.1.10 Hub Interface Subtractive Decode ......................................................104
AGP Memory Address Ranges...........................................................................104
4.2.1
AGP DRAM Graphics Aperture ...........................................................105
System Management Mode (SMM) Memory Range...........................................105
4.3.1
SMM Space Definition .........................................................................106
4.3.2
SMM Space Restrictions .....................................................................106
I/O Address Space..............................................................................................107
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Intel MCH Decode Rules and Cross-Bridge Address Mapping.........................107
4.5.1
Hub Interface Decode Rules ...............................................................107
4.5.2
AGP Interface Decode Rules ..............................................................108
System Bus .........................................................................................................109
5.1.1
Dynamic Bus Inversion........................................................................109
5.1.2
System Bus Interrupt Delivery .............................................................110
5.1.3
Upstream Interrupt Messages .............................................................110
System Memory Interface ...................................................................................110
5.2.1
SDR SDRAM Interface Overview........................................................110
5.2.2
Memory Organization and Configuration.............................................111
5.2.2.1
Configuration Mechanism For DIMMs ...............................111
5.2.2.1.1
Memory Detection and Initialization ...................111
5.2.2.1.2
SMBus Configuration and Access of the
Serial Presence Detect Ports .............................112
4.2
4.3
4.4
4.5
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Functional Description .....................................................................................................109
5.1
5.2
Intel 82845 MCH Datasheet
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