74LVC4066
Quad bilateral switch
Rev. 02 — 27 August 2007
Product data sheet
1. General description
The 74LVC4066 is a high-speed Si-gate CMOS device.
The 74LVC4066 provides four single pole, single-throw analog switch functions. Each
switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).
When nE is LOW, the analog switch is turned off.
Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise
and fall times across the entire V
CC
range from 1.65 V to 5.5 V.
2. Features
s
Wide supply voltage range from 1.65 V to 5.5 V
s
Very low ON resistance:
x
7.5
Ω
(typical) at V
CC
= 2.7 V
x
6.5
Ω
(typical) at V
CC
= 3.3 V
x
6
Ω
(typical) at V
CC
= 5 V
s
Switch current capability of 32 mA
s
High noise immunity
s
CMOS low-power consumption
s
Direct interface TTL-levels
s
Latch-up performance exceeds 250 mA
s
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
s
Enable inputs accept voltages up to 5 V
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
NXP Semiconductors
74LVC4066
Quad bilateral switch
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC4066D
74LVC4066PW
74LVC4066BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
SO14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
4. Functional diagram
1
13
4
5
8
6
11
12
1Y
1E
2Y
2E
3Y
3E
4Y
4E
1Z
2
1
2
1
13 #
4
3
#
9
#
10
8
6
11
12 #
(a)
#
5
#
1
X1
1
X1
1
X1
1
X1
(b)
1
2
2Z
3
13 #
4
5
1
3
3Z
9
8
6
1
9
4Z 10
11
12 #
1
10
mnb111
mnb112
Fig 1. Logic symbol
Fig 2. Logic symbol (IEEE/IEC)
Z
Y
E
V
CC
mna658
Fig 3. Logic diagram (one switch)
74LVC4066_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 27 August 2007
2 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
5. Pinning information
5.1 Pinning
terminal 1
index area
1Z
2Z
2Y
2E
2E
3E
GND
5
6
7
001aad117
1Y
1Z
2Z
2Y
1
2
3
4
14 V
CC
13 1E
12 4E
2
3
4
5
6
7
GND
3Y
8
14 V
CC
13 1E
12 4E
11 4Y
10 4Z
9
3Z
4066
11 4Y
10 4Z
9
8
3Z
3Y
GND
(1)
3E
1
1Y
4066
001aad118
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration for SO14 and TSSOP14
Fig 5. Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Y
1Z
2Z
2Y
2E
3E
GND
3Y
3Z
4Z
4Y
4E
1E
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
independent input/output
independent output/input
independent output/input
independent input/output
enable input (active HIGH)
enable input (active HIGH)
ground (0 V)
independent input/output
independent output/input
independent output/input
independent input/output
enable input (active HIGH)
enable input (active HIGH)
supply voltage
74LVC4066_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 27 August 2007
3 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
6. Functional description
Table 3.
Input nE
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Switch
OFF
ON
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
SK
V
SW
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
input clamping current
switch clamping current
switch voltage
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
−0.5
−0.5
−50
-
[2]
Max
+6.5
+6.5
-
±50
+6.5
±50
100
-
+150
500
Unit
V
V
mA
mA
V
mA
mA
mA
°C
mW
V
I
<
−0.5
V or V
I
< V
CC
+ 0.5 V
V
I
<
−0.5
V or V
I
< V
CC
+ 0.5 V
enable and disable mode
−0.5
< V
SW
< V
CC
+ 0.5 V
−0.5
-
-
−100
−65
T
amb
=
−40 °C
to +125
°C
[3]
-
The minimum input voltage rating may be exceeded if the input current rating is observed.
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
For SO14 packages: above 70
°C
derate linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
derate linearly with 4.5 mW/K.
74LVC4066_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 27 August 2007
4 of 22
NXP Semiconductors
74LVC4066
Quad bilateral switch
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
SW
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
[1]
[2]
[2]
[1]
Conditions
Min
1.65
0
0
−40
-
-
Typ
-
-
-
-
-
-
Max
5.5
5.5
V
CC
+125
20
10
Unit
V
V
V
°C
ns/V
ns/V
To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no
limit for the voltage drop across the switch.
Applies to control signal levels.
[2]
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
I
I
I
S(OFF)
input leakage
current
OFF-state
leakage
current
ON-state
leakage
current
pin nE; V
CC
= 5.5 V;
V
I
= 5.5 V or GND
V
I
= V
IH
or V
IL
; V
CC
= 5.5 V;
see
Figure 6
V
I
= V
IH
or V
IL
; V
CC
= 5.5 V;
see
Figure 7
[2]
−40 °C
to +85
°C
Min
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
±0.1
±0.1
Max
-
-
-
-
0.35V
CC
0.7
0.8
0.3V
CC
±5
±5
−40 °C
to +125
°C
Unit
Min
0.65V
CC
1.7
2.0
0.7V
CC
-
-
-
-
-
-
Max
-
-
-
-
0.7
0.8
0.3V
CC
±20
±20
V
V
V
V
V
V
V
µA
µA
0.35V
CC
V
[2]
I
S(ON)
[2]
-
±0.1
±5
-
±20
µA
I
CC
∆I
CC
supply current V
I
= V
CC
or GND; V
SW
= GND or
V
CC
; V
CC
= 5.5 V; I
O
= 0 A;
additional
pin nE; V
I
= V
CC
−
0.6 V; V
CC
= 5.5 V;
supply current V
SW
= GND or V
CC
[2]
-
-
0.1
5
10
500
-
-
40
5000
µA
µA
[2]
74LVC4066_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 27 August 2007
5 of 22
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