74LV138
3-to-8 line decoder/demultiplexer; inverting
Rev. 03 — 15 November 2007
Product data sheet
1. General description
The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC138 and 74HCT138.
The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted
address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive
active LOW outputs (Y0 to Y7).
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74LV138 devices and one inverter. The
74LV138 can be used as an eight output demultiplexer by using one of the active LOW
enable inputs as the data input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their appropriate active HIGH or LOW state.
2. Features
s
s
s
s
s
s
s
s
s
s
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
°C
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
s
s
NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV138N
74LV138D
74LV138DB
74LV138PW
74LV138BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
4. Functional diagram
DX
1
1
2
3
A0
A1
A2
Y0
Y1
Y2
Y3
4
5
6
E1
E2
E3
Y4
Y5
Y6
Y7
mna370
0
1
15
14
13
12
11
10
9
7
4
5
6
&
1
2
3
1
2
4
X/Y
0
1
2
3
4
5
6
15
14
13
12
11
10
9
7
0
G
2
0
7
15
14
13
12
11
10
9
7
2
3
2
3
4
4
5
6
&
5
6
7
EN
7
mna371
(a)
(b)
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LV138_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 November 2007
2 of 17
NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
Y0
1
2
3
A0
A1
A2
3-to-8
DECODER
ENABLE
EXITING
Y1
Y2
Y3
Y4
Y5
Y6
Y7
4
5
6
E1
E2
E3
mna372
15
14
13
12
11
10
9
7
Fig 3. Functional diagram
5. Pinning information
5.1 Pinning
74LV138
A0
A1
A2
E1
E2
E3
Y7
GND
1
2
3
4
16 V
CC
15 Y0
A1
14 Y1
13 Y2
A2
E1
E2
E3
6
7
8
001aad033
terminal 1
index area
2
3
4
5
6
7
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
Y6
9
138
5
12 Y3
11 Y4
10 Y5
9
Y6
V
CC(1)
8
GND
Y7
1
A0
001aah106
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16
Fig 5. Pin configuration DHVQFN16
74LV138_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 November 2007
3 of 17
NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
5.2 Pin description
Table 2.
Symbol
A0
A1
A2
E1
E2
E3
GND
Y0 to Y7
V
CC
Pin description
Pin
1
2
3
4
5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
Description
address input
address input
address input
enable input (active LOW)
enable input (active LOW)
enable input (active HIGH)
ground (0 V)
output
supply voltage
6. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care
Input
E1
H
X
X
L
L
L
L
L
L
L
L
E2
X
H
X
L
L
L
L
L
L
L
L
E3
X
X
L
H
H
H
H
H
H
H
H
A0
X
X
X
L
H
L
H
L
H
L
H
A1
X
X
X
L
L
H
H
L
L
H
H
A2
X
X
X
L
L
L
L
H
H
H
H
Output
Y0
H
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
H
L
H
H
H
H
H
Y3
H
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
H
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
74LV138_3
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
−0.5
-
-
-
-
−50
−65
Max
+7.0
±20
±50
±25
50
-
+150
Unit
V
mA
mA
mA
mA
mA
°C
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 November 2007
4 of 17
NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
Table 4.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
P
tot
Parameter
total power dissipation
DIP16 package
SO16 package
(T)SSOP16 package
DHVQFN16 package
[1]
[2]
[3]
[4]
[5]
Conditions
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
[5]
Min
-
-
-
-
Max
750
500
500
500
Unit
mW
mW
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 12 mW/K above 70
°C.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Parameter
supply voltage
[1]
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
Min
1.0
0
0
−40
-
-
-
-
Typ
3.3
-
-
+25
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
74LV138_3
−40 °C
to +85
°C
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
0.3V
CC
−40 °C
to +125
°C
Unit
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
V
V
V
V
V
V
V
0.3V
CC
V
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 15 November 2007
5 of 17
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