88E1000/88E1000S
Integrated 10/100/1000
Gigabit Ethernet Transceiver
Preliminary Information
Overview
Marvell’s Alaska
TM
Gigabit Ethernet Transceiver is a physi-
cal layer device for Ethernet 1000BASE-T, 100BASE-TX, and
10BASE-T applications. It is manufactured using standard
digital CMOS process and contains all the active circuitry
required to implement the physical layer functions to transmit
and receive data on standard CAT 5 unshielded twisted pair
cable.
The Alaska
TM
88E1000/88E1000S device has an IEEE
802.3 compliant Gigabit Media Independent Interface (GMII)
and a 10-bit (TBI) interface that connect directly to a
MAC/switch port. The 88E1000S operates in the same way
as the 88E1000, but it incorporates an additional proprietary
1.25 GHz SERDES (Serializer/Deserializer) interface that
reduces pin count for high port count applications. The SER-
DES interface may be connected directly to a fiber-optic
transceiver for 1000BASE-T/1000BASE-X media conversion
applications. Additionally, the 88E1000S may be used to
implement a 1000BASE-T GBIC (Gigabit Interface Con-
verter).
The 88E1000/88E1000S uses advanced mixed-signal pro-
cessing to perform equalization, echo and cross-talk cancel-
lation, data recovery, and error correction at a gigabit per
second data rate. Marvell’s advanced mixed-signal technol-
ogy allows the 88E1000/88E1000S to achieve robust perfor-
mance in noisy environments with low power dissipation.
Features
• IEEE 802.3 compliant 1000BASE-T, 100BASE-TX,
and 10BASE-T port
• Low power dissipation 1.8W
• IEEE 802.3 compliant GMII/MII
• Ten-bit interface option in 1000BASE-T mode
• Four-pin 1.25 GHz SERDES interface option
(88E1000S only)
• Automatic MDI/MDIX crossover for all 3 speeds of
operation including 100BASE-TX and 10BASE-T
• Automatic polarity correction
• IEEE 802.3u Auto-Negotiation with next page support
for automatic speed and duplex configuration
• Direct drive LED support
• Digital adaptive equalizer, echo cancellers, and
crosstalk cancellers
• Baseline wander correction
• On-chip transmit waveshaping
• Active internal hybrids for 1000BASE-T
• Supports low cost 25 MHz external clock source
• Supports both commercial and industrial temperature
ranges
• IEEE 1149.1 Standard Test Access Port (TAP) and
boundary scan compatible
• 0.18
µm
standard digital CMOS process
• 128-Pin PQFP package
1 0 /1 0 0 /1 0 0 0 M b/s
E th e rn e t M A C
A laska
T M
8 8 1 0 0 0 /8 8 E 1 0 0 0 S
M A C In te rfa ce O p tio n s
- G M II/M II
- TB I
- S E R D E S , 4 -P in S e ria l fo r 8 8 E 1 0 0 0 S O n ly
M
a
g
n
e
t
i
c
s
R J45
M e d ia Typ e s:
- 1 0 B A S E -T
- 1 0 0 B A S E -TX
- 1 0 0 0 B A S E -T
88E1000/88E1000S System Diagram
Doc. No. MV-S100153-00 Rev. I
Proprietary Information
Page 1
May 15, 2001
Marvell Company Confidential
88E1000/88E1000S
Integrated 10/100/1000 Gigabit Ethernet Transceiver
Document Conventions
The following name and usage conventions are used in this document:
Signal Range
A signal name followed by a range enclosed in brackets represents a range of logically related signals. The first
number in the range indicates the most significant bit (MSb) and the last number indicates the least significant
bit (LSb).
Example: TXD[7:0]
Active Low Signals
#
A # symbol at the end of a signal name indicates that the signal’s active state occurs when voltage is low.
Example: RESET#
Register Address
Register addresses are indicated with two fields. The decimal register address is followed by the bit range.
Example: 16.13:12 Receive FIFO Depth
Reserved
State Names
The contents of the register are reserved for internal use only or future use.
State names are indicated in
italic
font.
Example:
linkfail
Document Status
Advanced
Information
Preliminary
Information
Final
Information
This datasheet contains design specifications for initial product development. Specifications may change with-
out notice. Contact Marvell Field Application Engineers for more information.
This datasheet contains preliminary data, and a revision of this document will be published at a later date. Spec-
ifications may change without notice. Contact Marvell Field Application Engineers for more information.
This datasheet contains specifications on a product that is in final release. Specifications may change without
notice. Contact Marvell Field Application Engineers for more information.
No responsibility is assumed by Marvell Technology Group Limited either for use of this product, or for any infringements of patents and
trademarks, or other rights of third parties resulting from its use. No license is granted under any patents, patent rights, or trademarks of
Marvell Technology Group Limited. Marvell Technology Group Limited reserves the right to make changes in specifications at any time
without notice.Accordingly,thereaderiscautionedtoverifythatthereferencedspecificationiscurrentbeforefinalizinganydesign.
Revision Code: 1697
Document Status: Preliminary Information
Technical Publications: 1.0
Page 2
ã
Copyright
2001 Marvell Technology Group Limited. Do not duplicate without permission.
Proprietary Information
Doc. No. MV-S100153-00 Rev. I
Marvell Company Confidential
May 15, 2001
88E1000/88E1000S
Integrated 10/100/1000 Gigabit Ethernet Transceiver
Table of Contents
1. Signal Description ......................................................................................................................... 5
1.1 128-Pin Package .................................................................................................................. 5
1.2 Pin Description ..................................................................................................................... 7
1.3 128-Pin Signal Assignments - Alphabetical by signal name............................................... 17
2. Functional Description................................................................................................................ 19
2.1 MAC Interface..................................................................................................................... 20
2.2 Gigabit Media Independent Interface (GMII) and Media Independent Interface (MII) ........ 20
2.3 Ten-Bit Interface ................................................................................................................. 22
2.4 High Speed SERDES Interface .......................................................................................... 23
2.5 Synchronizing FIFO............................................................................................................ 23
2.6 Serial Management Interface ............................................................................................. 24
2.6.1 Programming Interrupts .......................................................................................... 25
2.7 Transmit and Receive Functions ........................................................................................ 26
2.7.1 Transmit Side Network Interface ............................................................................ 26
2.7.2 Encoder .................................................................................................................. 26
2.7.3 Receive Side Network Interface ............................................................................. 26
2.7.4 Decoder .................................................................................................................. 27
2.8 Clock Multiplier ................................................................................................................... 28
2.9 Initialization......................................................................................................................... 28
2.9.1 Hardware Reset ...................................................................................................... 28
2.9.2 Hardware Configuration Settings ........................................................................... 28
2.10 Power Supply ................................................................................................................... 28
2.11 Hardware Configuration.................................................................................................... 29
2.12 Auto-Negotiation............................................................................................................... 32
2.12.1 Configuring Auto-Negotiation Options .................................................................. 33
2.12.2 Next Page Exchanges .......................................................................................... 34
2.12.3 Register Update .................................................................................................... 34
2.12.4 Status Registers ................................................................................................... 34
2.13 MDI/MDIX Crossover........................................................................................................ 35
2.14 Polarity Correction ............................................................................................................ 35
2.15 LED Interface.................................................................................................................... 36
2.16 IEEE 1149.1 Controller..................................................................................................... 38
2.16.1 Bypass Instruction ................................................................................................ 38
2.16.2 Sample/Preload Instruction .................................................................................. 38
2.16.3 Boundary Scan Chain Order ................................................................................ 39
2.16.4 Extest Instruction .................................................................................................. 40
2.16.5 The Clamp Instruction .......................................................................................... 40
2.16.6 The HIGH-Z Instruction ........................................................................................ 40
3. Register Description ................................................................................................................... 41
4. Electrical Specifications ............................................................................................................. 59
4.1 Absolute Maximum Ratings................................................................................................ 59
4.2 Recommended Operating Conditions ................................................................................ 60
4.3 DC Electrical Characteristics .............................................................................................. 61
4.3.1 Current Consumption ............................................................................................. 61
4.3.2 Current Consumption ............................................................................................. 62
4.4 Digital Operating Conditions............................................................................................... 63
4.5 Internal Resistor Description .............................................................................................. 63
Doc. No. MV-S100153-00 Rev. I
Proprietery Information
Page 3
May 15, 2001
Marvell Company Confidential
88E1000/88E1000S
Integrated 10/100/1000 Gigabit Ethernet Transceiver
4.6 IEEE DC Transceiver Parameters ...................................................................................... 64
4.7 DC Reference Points for AC Timing ................................................................................... 65
4.8 AC Electrical Specifications ................................................................................................ 66
4.8.1 Reset Timing ........................................................................................................... 66
4.8.2 Clock Timing ........................................................................................................... 67
4.9 GMII Interface Timing ......................................................................................................... 68
4.9.1 1000BASE-T GMII Transmit Timing ....................................................................... 68
4.9.2 1000BASE-T GMII Receive Timing ........................................................................ 69
4.10 MII Interface Timing .......................................................................................................... 70
4.10.1 100BASE-T MII Transmit Timing .......................................................................... 70
4.10.2 10BASE-T MII Transmit Timing ............................................................................ 70
4.10.3 100BASE-T MII Receive Timing ........................................................................... 71
4.10.4 10BASE-T MII Receive Timing ............................................................................. 71
4.11 TBI Interface Timing ......................................................................................................... 72
4.11.1 TBI Transmit Timing ............................................................................................. 72
4.11.2 TBI Receive Timing .............................................................................................. 73
4.12 GMII/MII Interface Latency Timing.................................................................................... 74
4.12.1 1000BASE-T GMII Transmit Latency Timing ........................................................ 74
4.12.2 100BASE-TX MII Transmit Latency Timing .......................................................... 74
4.12.3 10BASE-T MII Transmit Latency Timing .............................................................. 75
4.12.4 1000BASE-T GMII Receive Latency Timing ......................................................... 76
4.12.5 100BASE-TX MII Receive Latency Timing ........................................................... 76
4.12.6 10BASE-T MII Receive Latency Timing ............................................................... 77
4.12.7 TBI Transmit Latency Timing ................................................................................ 78
4.12.8 TBI Receive Latency Timing ................................................................................. 79
4.12.9 SERDES Interface Transmit Latency Timing ........................................................ 80
4.12.10 SERDES Interface Receive Latency Timing ....................................................... 81
4.12.11 SERDES AC Characteristics .............................................................................. 82
4.12.12 SERDES Receiver AC Specifications ................................................................. 82
4.12.13 Serial Management Interface Timing .................................................................. 83
4.12.14 JTAG Timing ....................................................................................................... 84
4.13 IEEE AC Transceiver Parameters .................................................................................... 85
Mechanical Drawings .................................................................................................................. 86
5.1 128-Pin PQFP Package...................................................................................................... 86
MDI Interface Circuitry................................................................................................................. 87
Application Examples.................................................................................................................. 88
Order Information ........................................................................................................................ 90
5.
6.
7.
8.
Page 4
Proprietery Information
Doc. No. MV-S100153-00 Rev. I
Marvell Company Confidential
May 15, 2001
88E1000/88E1000S
Integrated 10/100/1000 Gigabit Ethernet Transceiver
1. Signal Description
1.1
128-Pin Package
RXD5
RXD6
RXD7
DVDDH
VDDO
125CLK
VSS
VSS
NC
DVDDH
MDC
MDIO
NC
INT#
LED_LINK10
DVDDL
VSS
VSS
LED_LINK100
VDDO
NC
LED_LINK1000
LED_DUPLEX
LED_RX
LED_TX
VSS
CONFIG0
CONFIG1
NC
CONFIG2
CONFIG3
CONFIG4
TDO
TDI
VSS
VSS
VSS
RXD4
RXD3
VSS
RXD2
VSS
VDDO
VDDO
VSS
RXD1
RXD0
RX_DV
RX_CLK
VSS
VDDO
VDDO
VSS
RX_ER
COL
CRS
TX_CLK
TX_ER
GTX_CLK
TX_EN
VSS
TXD0
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VSS
VSS
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
88E1000
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AVDDL
VSS
MDI[3]-
MDI[3]+
VSS
AVDDL
VSS
MDI[2]-
MDI[2]+
VSS
HSDAC-
HSDAC+
AVDDH
VSS
NC
AVDDL
VSS
MDI[1]-
MDI[1]+
VSS
AVDDL
VSS
MDI[0]-
MDI[0]+
VSS
RSET
Figure 1 shows the signal assignments for the Alaska
TM
chip manufactured in the 128-pin package.
Doc. No. MV-S100153-00 Rev. I
VSS
VSS
AVDDH
AVDDL
NC
NC
NC
NC
DVDDH
VSS
VSS
NC
DVDDH
DVDDL
VSS
NC
TXD1
NC
TXD2
TXD3
VSS
VSS
TXD4
TXD5
NC
TXD6
TXD7
VSS
VDDO
XTAL1
XTAL2
RESET#
NC
TCK
TMS
TRST#
NC
VSS
(Top View)
Figure 1: Alaska
TM
Integrated 10/100/1000 Gigabit Ethernet Transceiver
Proprietary Information
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May 15, 2001
Marvell Company Confidential
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