74AHCU04
Hex inverter
Rev. 03 — 14 November 2007
Product data sheet
1. General description
The 74AHCU04 is high-speed Si-gate CMOS devices and is pin compatible with low
power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.
The 74AHCU04 is a general purpose hex inverter. Each of the six inverters is a single
stage.
2. Features
s
s
s
s
Low power dissipation
Balanced propagation delays
Inputs accepts voltages higher than V
CC
ESD protection:
x
HBM JESD22-A114E: exceeds 2000 V
x
MM JESD22-A115-A: exceeds 200 V
x
CDM JESD22-C101C: exceeds 1000 V
s
Multiple package options
s
Specified from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74AHCU04D
74AHCU04PW
74AHCU04BQ
Name
Description
Version
Type number
−40 °C
to +125
°C
SO14
−40 °C
to +125
°C
TSSOP14
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
SOT762-1
−40 °C
to +125
°C
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74AHCU04
Hex inverter
4. Functional diagram
1
1
2
1
1A
1Y
2
3
1
4
3
2A
2Y
4
5
1
6
5
3A
3Y
6
9
1
8
9
4A
4Y
8
11
5A
5Y
10
11
1
10
13
6A
6Y
12
13
1
mna343
12
A
Y
mna045
mna342
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one inverter)
5. Pinning information
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
9
7
GND
4Y
8
4A
terminal 1
index area
1Y
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
001aac441
2
3
4
5
6
14 V
CC
13 6A
12 6Y
2A
2Y
3A
3Y
04
11 5A
10 5Y
9
8
4A
4Y
GND
(1)
1
1A
04
001aac442
Transparent top view
(1) The die substrate is attached to the exposed die pad
using conductive die attach material. It can not be
used as a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
5.1 Pin description
Table 2.
Symbol
1A
1Y
2A
2Y
74AHCU04_3
Pin description
Pin
1
2
3
4
Description
data input
data output
data input
data output
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
2 of 14
NXP Semiconductors
74AHCU04
Hex inverter
Table 2.
Symbol
3A
3Y
GND
4Y
4A
5Y
5A
6Y
6A
V
CC
Pin description
…continued
Pin
5
6
7
8
9
10
11
12
13
14
Description
data input
data output
ground (0 V)
data output
data input
data output
data input
data output
data input
supply voltage
6. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level
Input
nA
L
H
Output
nY
H
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
I
IK
V
I
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
−0.5
V
[1]
Min
−0.5
−20
−0.5
-
-
-
−75
−65
Max
+7.0
-
+7.0
±20
±25
75
-
+150
500
Unit
V
mA
V
mA
mA
mA
mA
°C
mW
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
−0.5
V < V
O
< V
CC
+ 0.5 V
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
°C
the value of P
tot
derates linearly with 8 mW/K.
For TSSOP14 packages: above 60
°C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
the value of P
tot
derates linearly with 4.5 mW/K.
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
3 of 14
NXP Semiconductors
74AHCU04
Hex inverter
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
Conditions
Min
2.0
0
0
−40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
Unit
V
V
V
°C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol
V
IH
Parameter
HIGH-level
input voltage
Conditions
Min
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
−50 µA;
V
CC
= 2.0 V
I
O
=
−50 µA;
V
CC
= 3.0 V
I
O
=
−50 µA;
V
CC
= 4.5 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
I
O
=
−8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
µA;
V
CC
= 2.0 V
I
O
= 50
µA;
V
CC
= 3.0 V
I
O
= 50
µA;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
1.7
2.4
4.4
-
-
-
1.8
2.7
4.0
2.58
3.94
-
-
-
-
-
-
-
-
25
°C
Typ
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3
Max
-
-
-
0.3
0.6
1.1
-
-
-
-
-
0.2
0.3
0.5
0.36
0.36
0.1
2.0
10
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
1.7
2.4
4.4
-
-
-
1.8
2.7
4.0
2.48
3.8
-
-
-
-
-
-
-
-
Max
-
-
-
0.3
0.6
1.1
-
-
-
-
-
0.2
0.3
0.5
0.44
0.44
1.0
20
10
Min
1.7
2.4
4.4
-
-
-
1.8
2.7
4.0
2.4
3.7
-
-
-
-
-
-
-
-
Max
-
-
-
0.3
0.6
1.1
-
-
-
-
-
0.2
0.3
0.5
0.55
0.55
2.0
40
10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
pF
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
74AHCU04_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
4 of 14
NXP Semiconductors
74AHCU04
Hex inverter
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see
Figure 7.
Symbol
t
pd
Parameter
propagation
delay
Conditions
Min
nA to nY; see
Figure 6
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF
C
L
= 50 pF
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
C
PD
power
dissipation
capacitance
C
L
= 50 pF; f
i
= 1 MHz;
V
I
= GND to V
CC
[4]
[3]
[1]
[2]
25
°C
Typ
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
-
-
-
-
-
3.0
3.4
2.4
3.5
9.1
7.1
10.6
5.5
7.0
-
1.0
1.0
1.0
1.0
-
8.5
12.0
6.5
8.0
-
1.0
1.0
1.0
1.0
-
9.0
13.5
7.0
9.0
-
ns
ns
ns
ns
pF
[1]
[2]
[3]
[4]
t
pd
is the same as t
PLH
and t
PHL
.
Typical values are measured at V
CC
= 3.3 V.
Typical values are measured at V
CC
= 5.0 V.
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
11. Waveforms
V
I
nA input
GND
t
PHL
V
OH
nY output
V
OL
V
M
V
M
mna344
V
M
V
M
V
CC
t
PLH
PULSE
GENERATOR
VI
VO
DUT
RT
CL
50 pF
mna034
V
M
= 0.5
×
V
CC
; V
I
= GND to V
CC
.
Test data is given in
Table 7.
Definitions for test circuit:
C
L
= Load capacitance including jig and probe
capacitance.
R
T
= Termination resistance should be equal to
output impedance Z
o
of the pulse generator.
Fig 6. The input (nA) to output (nY) propagation delay
times
74AHCU04_3
Fig 7. Load circuit for switching times
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 14 November 2007
5 of 14
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