SyncMOS Technologies International, Inc.
SM8951A/8952A
8-Bits Micro-controller
With 4/8KB flash embedded
Product List
SM8951A/8952AL25, 25MHz 4/8KB internal flash MCU
SM8951A/8952AC25, 25MHz 4/8KB internal flash MCU
SM8951A/8952AC40, 40MHz 4/8KB internal flash MCU
Features
Working Voltage: 3.0V ~ 3.6V For L Version.
4.5V ~ 5.5V For C Version.
General 8052 family compatible
12 clocks per machine cycle
4/8K internal flash memory
256 bytes data RAM
2/3 16 bit timers/counters
Four 8-bit I/O ports
Full duplex serial channel
Bit operation instruction
Industrial Level
8-bit unsigned division
8-bit unsigned multiply
BCD arithmetic
Direct addressing
Indirect addressing
Nested interrupt
Two priority level interrupt
A serial I/O port
Power save modes:
Idle mode and Power down mode
Code protection function
One watch dog timer(WDT)
Low EMI (inhibit ALE)
Description
The SM8951A/8952A series product is an 8-bit single
chip micro controller with 4/8 KB flash embedded. It
provides hard-ware features and a powerful instruction
set, necessary to make it a versatile and cost effective
controller for those applications demand up to 32 I/O
pins or need up to 4/8 KB flash memory either for
program or for data or mixed.
To program the flash block, a commercial programmer
is capable to do it.
Ordering Information
yymmv
SM8951A/8952AihhkL
yy: year, ww: month
v: version identifier{ , A, B,…}
i: process identifier {L=3.0V~3.6V,C=4.5V~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
L:PB Free identifier
{No text is Non-PB Free，”P”is PB Free}
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP
Pin / Pad
Configuration
Page 2
Page 2
Page 2
Dimension
Page 13
Page 14
Page 15/16
Taiwan
6F, No.10-2 Li- Hsin 1st Road ,
Science-based Industrial Park,
Hsinchu, Taiwan 30078
TEL: 886-3-567-1820
886-3-567-1880
FAX: 886-3-567-1891
886-3-567-1894
Specifications subject to change without notice contact your sales representatives for the most recent information.
1
Ver 2.1
SM8951A/8952A 08/2006
SyncMOS Technologies International, Inc.
SM8951A/8952A
8-Bits Micro-controller
With 4/8KB flash embedded
Pin Configuration
Specifications subject to change without notice contact your sales representatives for the most recent information.
2
Ver 2.1
SM8951A/8952A 08/2006
SyncMOS Technologies International, Inc.
SM8951A/8952A
8-Bits Micro-controller
With 4/8KB flash embedded
Block Diagram
Specifications subject to change without notice contact your sales representatives for the most recent information.
3
Ver 2.1
SM8951A/8952A 08/2006
SyncMOS Technologies International, Inc.
SM8951A/8952A
8-Bits Micro-controller
With 4/8KB flash embedded
Pin Description
40L
PDIP
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
44L
QFP
Pin#
40
41
42
43
44
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
44L
PLCC
Pin#
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
Symbol
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RES
P3.0/RXD
P3.1/TXD
P3.2/#INT0
P3.3/#INT1
P3.4/T0
P3.5/T1
P3.6/#WR
P3.7/#RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
#PSEN
ALE
#EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
Active
I/O
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
Names
bit 0 of port 1
bit 1 of port 1
bit 2 of port 1
bit 3 of port 1
bit 4 of port 1
bit 5 of port 1
bit 6 of port 1
bit 7 of port 1
Reset
bit 0 of port 3 & Receiver data
bit 1 of port 3 & Transmit data
bit 2 of port 3 & low true interrupt 0
bit 3 of port 3 & low true interrupt 1
bit 4 of port 3 & Timer 0
bit 5 of port 3 & Timer 1
bit 6 of port 3 & external memory write
bit 7 of port 3 & external memory Read
Crystal out
Crystal in
Sink Voltage, Ground
bit 0 of port 2 & bit 8 of external memory address
bit 1 of port 2 & bit 9 of external memory address
bit 2 of port 2 & bit 10 of external memory address
bit 3 of port 2 & bit 11 of external memory address
bit 4 of port 2 & bit 12 of external memory address
bit 5 of port 2 & bit 13 of external memory address
bit 6 of port 2 & bit 14 of external memory address
bit 7 of port 2 & bit 15 of external memory address
program storage enable
address latch enable
external access
bit 7 of port 0 & data/address bit 7 of external memory
bit 6 of port 0 & data/address bit 6 of external memory
bit 5 of port 0 & data/address bit 5 of external memory
bit 4 of port 0 & data/address bit 4 of external memory
bit 3 of port 0 & data/address bit 3 of external memory
bit 2 of port 0 & data/address bit 2 of external memory
bit 1 of port 0 & data/address bit 1 of external memory
bit 0 of port 0 & data/address bit 0 of external memory
Drive Voltage, +5 Vcc
H
L/-
L/-
L/-
L/-
L
-
L
Specifications subject to change without notice contact your sales representatives for the most recent information.
4
Ver 2.1
SM8951A/8952A 08/2006
SyncMOS Technologies International, Inc.
SM8951A/8952A
8-Bits Micro-controller
With 4/8KB flash embedded
SFR Memory Map
$F8
$F0
$E8
$E0
$D8
$D0
$C8
$C0
$B8
$B0
$A8
$A0
$98
$90
$88
$80
B
ACC
PSW
T2CON
IP
P3
IE
P2
SCON
P1
TCON
P0
RC2L
RC2H
TL2
TH2
SCONF
$FF
$F7
$EF
$E7
$DF
$D7
$CF
$C7
$BF
$B7
$AF
$A7
$9F
$97
$8F
$87
SBUF
TMOD
SP
TL0
DPL
TL1
DPH
TH0
TH1
WDTC
PCON
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM8951A/8952A
Extension Function Description
Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The
WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing
software dead loop or runaway. The WDT function can help user software recover from abnormal software condition.
The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by
software periodically clearing the WDT counter.
The SM8951/8952 WDT has selectable divider input for the time base source clock. To select the divider input, the
setting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to
count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0
automatically when SM8958A been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the
content of the 16-bit counter and let the counter re-start to count from the beginning.
Specifications subject to change without notice contact your sales representatives for the most recent information.
5
Ver 2.1
SM8951A/8952A 08/2006
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