WSF128K16-XXX
HI-RELIABILITY PRODUCT
128K
X
16 SRAM/FLASH MODULE, SMD 5962-96900
FEATURES
s
Access Times of 35ns (SRAM) and 70ns (FLASH)
s
Access Times of 70ns (SRAM) and 120ns (FLASH)
s
Packaging
• 66-pin, PGA Type, 1.075 inch square HIP, Hermetic
Ceramic HIP (Package 400)
• 66-pin, PGA Type, 1.185 inch square HIP, Hermetic
Ceramic HIP (Package 401)
• 68 lead, Hermetic CQFP (G2), 22mm (0.880 inch) square
(Package 500). Designed to fit JEDEC 68 lead 0.990” CQFJ
footprint (Fig. 2)
s
128Kx16 SRAM
s
128Kx16 5V FLASH
s
Organized as 128Kx16 of SRAM and 128Kx16 of Flash
Memory with separate Data Buses
s
Both blocks of memory are User Configurable as 256Kx8
s
Low Power CMOS
s
Commercial, Industrial and Military Temperature Ranges
s
TTL Compatible Inputs and Outputs
s
Built-in Decoupling Caps and Multiple Ground Pins for
Low Noise Operation
s
Weight - 13 grams typical
FLASH MEMORY FEATURES
s
10,000 Erase/Program Cycles
s
Sector Architecture
• 8 equal size sectors of 16K bytes each
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
s
5 Volt Programming; 5V
±
10% Supply
s
Embedded Erase and Program Algorithms
s
Hardware Write Protection
s
Page Program Operation and Internal Program Control Time.
Note: Programming information available upon request.
FIG.1
1
SD
8
SD
9
SD
10
A
13
A
14
A
15
A
16
NC
SD
0
SD
1
SD
2
11
PIN CONFIGURATION FOR WSF128K16-XHX
AND WSF128K16-XH1X
TOP VIEW
12
SWE
2
SCS
2
GND
SD
11
A
10
A
11
A
12
V
CC
SCS
1
NC
SD
3
22
33
23
SD
15
SD
14
SD
13
SD
12
OE
NC
SWE
1
SD
7
SD
6
SD
5
SD
4
FD
8
FD
9
FD
10
A
6
A
7
NC
A
8
A
9
FD
0
FD
1
FD
2
44
34
V
CC
FCS
2
FWE
2
FD
11
A
3
A
4
A
5
FWE
1
FCS
1
GND
FD
3
55
45
FD
15
FD
14
FD
13
FD
12
A
0
A
1
A
2
FD
7
FD
6
FD
5
FD
4
66
8
8
8
PIN DESCRIPTION
FD
0-15
Flash Data Inputs/Outputs
56
SD
0-15
SRAM Data Inputs/Outputs
A
0-16
SWE
1-2
SCS
1-2
OE
V
CC
GND
NC
FWE
1-2
Address Inputs
SRAM Write Enable
SRAM Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enable
Flash Chip Select
BLOCK DIAGRAM
S W E
1
S CS
1
OE
A
0
-
16
128K x 8
SRAM
128K x 8
SRAM
128K x 8
FLASH
S W E
2
S CS
2
F W E
1
F CS
1
FCS
1-2
F W E
2
F CS
2
128K x 8
FLASH
8
SD
0-7
SD
8-15
FD
0-7
FD
8-15
July 1998 Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WSF128K16-XXX
FIG. 2
PIN CONFIGURATION FOR WSF128K16-XG2X
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
FCS
1
GND
FCS
2
SWE
1
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
FD
0-15
Flash Data Inputs/Outputs
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
SD
0
SD
1
SD
2
SD
3
SD
4
SD
5
SD
6
SD
7
GND
SD
8
SD
9
SD
10
SD
11
SD
12
SD
13
SD
14
SD
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
SCS
1
SCS
2
NC
FWE
1
FWE
2
A
11
A
12
A
13
A
14
A
15
A
16
OE
V
CC
SWE
2
SD
0-15
SRAM Data Inputs/Outputs
FD
0
FD
1
FD
2
FD
3
FD
4
FD
5
FD
6
FD
7
GND
FD
8
FD
9
FD
10
FD
11
FD
12
FD
13
FD
14
FD
15
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
NC
NC
A
0-16
SWE
1-2
SCS
1-2
0.940"
Address Inputs
SRAM Write Enable
SRAM Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enable
Flash Chip Select
OE
V
CC
GND
NC
FWE
1-2
FCS
1-2
The WEDC 68 lead G2 CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2 has the TCE and lead
inspection advantage of the
CQFP form.
BLOCK DIAGRAM
S W E
1
S CS
1
OE
A
0
-
16
128K x 8
SRAM
128K x 8
SRAM
128K x 8
FLASH
128K x 8
FLASH
S W E
2
S CS
2
F W E
1
F CS
1
F W E
2
F CS
2
8
8
8
8
SD
0-7
SD
8-15
FD
0-7
FD
8-15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
WSF128K16-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Parameter
Flash Data Retention
Flash Endurance (write/erase cycles)
NOTES:
1. Stresses above the absolute maximum rating may cause permanent damage
to the device. Extended operation at the maximum levels may degrade
performance and affect reliability.
10 years
10,000
Test
OE Capacitance
F/S WE 1-2 Capacitance
F/S CS 1-2 Capacitance
SD
0
-
15
/FD
0
-
15
Capacitance
A
0
- A
16
Capacitance
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
7.0
150
7.0
Unit
°C
°C
V
°C
V
SCS
H
L
L
L
OE
X
L
H
X
SRAM TRUTH TABLE
SWE
X
H
H
L
Mode
Standby
Read
Read
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
CAPACITANCE
(T
A
= +25°C)
Symbol
C
OE
C
WE
C
CS
C
I
/
O
C
AD
Condition
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
Max
50
20
20
20
50
Unit
pF
pF
pF
pF
pF
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
IH
V
IL
Min
4.5
2.2
-0.5
Max
5.5
V
CC
+ 0.3
+0.8
Unit
V
V
V
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
SRAM Operating Supply Current x 16 Mode
Standby Current
SRAM Output Low Voltage
SRAM Output High Voltage
Flash V
CC
Active Current for Read (1)
Flash V
CC
Active Current for Program or
Erase (2)
Flash Output Low Voltage
Flash Output High Voltage
Flash Output High Voltage
Flash Low V
CC
Lock Out Voltage
Symbol
I
LI
I
LO
I
CCx16
I
SB
V
OL
V
OH
I
CC1
I
CC2
V
OL
V
OH1
V
OH2
V
LKO
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
SCS = V
IH
, OE = V
IH,
V
OUT
= GND to V
CC
SCS = V
IL
, OE = FCS = V
IH,
f = 5MHz, V
CC
= 5.5
FCS = SCS = V
IH
, OE = V
IH,
f = 5MHz, V
CC
= 5.5
I
OL
= 2.1mA, V
CC
= 4.5
I
OH
= -1.0mA, V
CC
= 4.5
FCS = V
IL
, OE = SCS = V
IH
FCS = V
IL
, OE = SCS = V
IH
I
OL
= 12.0mA, V
CC
= 4.5
I
OH
= -2.5 mA, V
CC
= 4.5
I
OH
= -100
µA,
V
CC
= 4.5
0.85 x V
CC
V
CC
-0.4
3.2
2.4
100
130
0.45
Min
Max
10
10
360
40
0.4
Unit
µA
µA
mA
mA
V
V
mA
mA
V
V
V
V
NOTES:
1. The I
CC
current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WSF128K16-XXX
SRAM AC CHARACTERISTICS
(V
CC
= 5.0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
1
1
1
1
SRAM AC CHARACTERISTICS
(V
CC
= 5.0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold from Write Time
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
-35
Min Max
35
35
0
35
20
3
0
20
20
-70
Unit
Min Max
70
70
5
70
35
5
5
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
-35
Min Max
35
25
25
20
25
0
0
4
20
0
0
70
60
60
30
50
5
5
5
-70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
ns
t
WHZ
1
t
DH
1. This parameter is guaranteed by design but not tested.
1. This parameter is guaranteed by design but not tested.
FIG. 3
AC TEST CIRCUIT
Current Source
I
OL
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
D.U.T.
V
Z
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
≈
1.5V
Output Timing Reference Level
C
eff
= 50 pf
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
WSF128K16-XXX
FIG. 4 SRAM
TIMING WAVEFORM - READ CYCLE
ADDRESS
t
RC
t
AA
SCS
t
RC
ADDRESS
t
ACS
t
CLZ
SOE
t
CHZ
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 1, (SCS = OE = V
IL
, SWE = V
IH
)
READ CYCLE 2, (SWE = V
IH
)
FIG. 5 SRAM
WRITE CYCLE - SWE CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
SCS
t
AH
t
AS
SWE
t
WP
t
OW
t
WHZ
t
DW
t
DH
DATA I/O
DATA VALID
WRITE CYCLE 1, SWE CONTROLLED
FIG. 6 SRAM
WRITE CYCLE - SCS CONTROLLED
t
WC
ADDRESS
WS32K32-XHX
t
CW
t
AH
t
AS
SCS
t
AW
t
WP
SWE
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, SCS CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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