BLOCK DIAGRAM:
Switch Core
Inputs [143:0]
EQ
EQ
VSC3040
Programming Interface
F E AT U R E S :
11 Gbps 144 × 144 strictly nonblocking switch matrix with multicast and
output striping programming modes
Input signal equalization (ISE) with programmable control globally or on
a per-channel basis
Adjustable output pre-emphasis EQ
Differential current mode logic (CML) data output driver
Protocol-independent switching and data transmission
45 mm × 45 mm, 1.27 mm pin pitch, 1072-pin BGA package
Parallel and serial programming modes for configuration and monitoring
Software control to optimize power dissipation
BENEFITS:
1.584 Tbps aggregate bandwidth in a single chip for
network switching and video systems
Addresses system-level and board-level signal integ
intersymbol interface (ISI) jitter issues
EQ and drive flexibility for driving boards, backplane
Convenient I/O flexibility for interfacing with multiple
Can be used with latest storage, Ethernet, and netw
Layout-friendly package and pinout for easier PCB d
Programming and control convenience
Control and lower overall power when ports are not
A P P L I C AT I O N S :
High-definition digital broadcast video systems
Multi-service provisioning platforms (MSPPs)
Mixed TDM/packet switching systems
High-speed storage, Ethernet, and networking equipment
DWDM switching systems
High-speed automated test equipment
VSC3040
equiqment applications. Combining the 11 Gbps per
port bandwidth and 144 × 144 switch matrix enables
a breakthrough 1.5 Tbps capacity in a single device.
The VSC3040 fully non-blocking switch core is programmed using a
multimode port interface that allows random access programming of each
I/O port. Each VSC3040 data output can be programmed to connect to
any of its inputs. The signal path through the device is fully asynchronous,
eliminating restrictions on the phase, frequency, or signal pattern of any
input.
switched-current driver with on-die termina
terminated on-die, using 100
Ω
resistors betwe
inputs with a common connection to an inte
facilitates AC-coupling to the switch inputs.
Core programming for the VSC3040 device
port-by-port basis, or multiple program assignm
issued simultaneously. The entire device
straight-through, multicast, or other configuratio
be powered down to allow efficient use of the s
require only a subset of the available I/O c
enabled in the software by programming individ
power-down code.
B A C K P L A N E A P P L I C AT I O N :
Line Cards
OE
FPGA/
ASIC
B
a
c
k
p
l
a
n
e
Central Switch
VSC3040
S P E C I F I C AT I O N S :
11 Gbps NRZ per-channel data rate
2.5 V power supply (2.5 V or 3.3 V program port power supply)
2.5 V or 3.3 V CMOS TTL-compatible I/O
Differential CML I/O with integrated termination impedance
Trademarks
Vitesse, ASIC-Friendly, FibreTimer, TimeStream, Snoop Loop, Super FEC, FOCUSConnect, Meigs-II, Meigs-IIe, Lansing, Campbell-I, Barrington,
PaceMaker, HOVCAT48, HOVCAT48e, HOVCAT192, HOVCAT192e, Micro PHY, FOCUS32, FOCUS16, IQ2200, NexSAS, VersaCAT, GigaStream, HawX,
SparX, StaX, VstaX, SimpliPHY,VeriPHY, ActiPHY, XFP PRO, SFP PRO, Smart-LINK, OctalMAC, EQ Technology are trademarks in the United States and/or
other jurisdictions of Vitesse Semiconductor Corporation. All other trademarks or registered trademarks mentioned herein are the property of their respective
holders.
Copyright © 2006
Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its products or specifications to improve performance, reliability or
manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is
subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by
Vitesse for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent
right of any manufacturer.
TM
741 C
Cam
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