1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name
X
0
- X
15
Y
0 -
Y
15
/
P
0
- P
15
P
16
- P
31
OEL
OEP
X
M,
Y
M
RND
O
I
I
I
I
I/O
I
I/O
Data Inputs
Y
0 -
Y
15
are data inputs
P
0
- P
15
are LSP register output, enabled when
OEL
= 0
Data Output (LSP or MSP)
Output enable control for LSP (least significant product). When LOW enables P
0
- P
15
. When HIGH P
0
- P
15
tristated.
Output enable control for MSP (most significant product). When LOW enables P
16
- P
31.
When HIGH P
16
- P
31
tristated.
Mode control for each data word. LOW designates unsigned data input and HIGH designates two’s complement.
“Round” control for rounding of MSP. When HIGH, 1 is added to the most significant bit of LSP. This signal is affected by the state of FA pin.
When FA = 1 and RND = 1, 1 is added to the 2
-15
bit (P
15
). When RND = 1 and FA = 0, 1 is added to the 2
-16
bit (P
14
). The RND input is
registered. It is clocked on the rising edge of the logical OR of CLKX and CLKY. Rounding always occurs in the positive direction which may
introduce a systematic bias.
MSPSEL
FA
FT
CLKX
CLKY
CLKL
CLKM
I
I
I
I
I
I
I
When LOW, MSP is output on P
16
- P
31
lines. When HIGH, LSP is output on P
16
- P
31.
Format adjust control. When HIGH, a full 32 bit product is selected. When LOW, a left shifted 31 bit product is selected with the sign bit
replicated in the LSP. FA is normally HIGH, except for certain fractional two’s complement applications (see multiplier input / output formats).
Flow through control. When HIGH, both MSP and LSP registers are by-passed.
X register clock input. Also clocks RND register.
Y register clock input. Also clocks RND register.
LSP register clock input.
MSP register clock input.
Description
3
IDT7216L
16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5V ± 10%
Symbol
V
IH
V
IL
I
LI
I
LO
I
CC
I
CCQ1
I
CCQ2
I
CC
/f
(2,3)
V
OH
V
OL(4)
I
OS
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Quiescent Power Supply Current
Quiescent Power Supply Current
Increase in Power Supply Current
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max., V
IN
= 0 to V
CC
V
CC
= Max.,
OE
= 2V, V
OUT
= 0 to V
CC
V
CC
= Max., Outputs Disabled, f = 10MHz
(2)
V
IN
≥
V
IH,
V
IN
≤
V
IL
V
IN
≥
V
CC
- 0.2V, V
IN
≤
0.2V
V
CC
= Max., Outputs Disabled
V
CC
= Min., I
OH
= –2mA
V
CC
= Min., I
OL
= 8mA
V
CC
= Max., V
O
= GND
Min.
2
—
—
—
—
—
—
—
2.4
—
-20
Typ.
(1)
—
—
—
—
40
20
4
—
—
—
—
Max.
—
0.8
10
10
80
40
20
4
—
0.4
-120
Unit
V
V
µA
µA
mA
mA
mA
mA/MHz
V
V
mA
NOTES:
1. Typical implies V
CC
= 5V and T
A
= +25°C.
2. I
CC
is measured at 10MHz and V
IN
= 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
I
CC
= 80+ 4(f –10)mA; for the military range, I
CC
= 100 + 6(f –10). f = operating frequency in MHz and f = 1/t
MC
.
3. For frequencies greater than 10MHz, guaranteed by design, not production tested.
4. I
OL
= 4mA for t
MC
>65ns.
4
IDT7216L
16 x 16 PARALLEL CMOS MULTIPLIERS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5V ± 10%
7216L16
Symbol
t
MUC
t
MC
t
S
t
H
t
PWH
t
PWL
t
PDSEL
t
PDP
t
PDY
t
ENA
t
DIS
t
HCL
Parameter
Unclocked Multiply Time
(4)
Clocked Multiply Time
(4)
X, Y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width HIGH
Clock Pulse Width LOW
MSPSEL
to Product Out
(4)
Output Clock to P
(4)
Output Clock to Y
(4)
3-State Enable Time
3-State Disable Time
(2)
Clock LOW Hold Time CLKXY Relative to CLKML
(1,3)
Min.
2
2
10
1
7
7
2
2
2
—
—
0
Max.
25
16
—
—
—
—
15
15
15
15
15
—
2
2
11
1
9
9
2
2
2
—
—
0
7216L20
Min.
Max.
30
20
—
—
—
—
18
18
18
18
18
—
7216L25
Min.
2
2
12
2
10
10
2
2
2
—
—
0
Max.
38
25
—
—
—
—
20
20
20
20
20
—
7216L35
Min.
2
2
12
3
10
10
2
2
2
—
—
0
Max.
55
35
—
—
—
—
25
25
25
25
22
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7216L45
Symbol
t
MUC
t
MC
t
S
t
H
t
PWH
t
PWL
t
PDSEL
t
PDP
t
PDY
t
ENA
t
DIS
t
HCL
Parameter
Unclocked Multiply Time
(4)
Clocked Multiply Time
(4)
X, Y, RND Set-up Time
X, Y, RND Hold Time
Clock Pulse Width HIGH
Clock Pulse Width LOW
MSPSEL
to Product Out
(4)
Output Clock to P
(4)
Output Clock to Y
(4)
3-State Enable Time
3-State Disable Time
(2)
Clock LOW Hold Time CLKXY Relative to CLKML
(1,3)
Min.
2
2
15
3
15
15
2
2
2
—
—
0
Max.
65
45
—
—
—
—
25
25
25
25
22
—
7216L55
Min.
2
2
20
3
15
20
2
2
2
—
—
0
Max.
75
55
—
—
—
—
25
30
30
30
25
—
7216L65
Min.
2
2
20
3
15
20
2
2
2
—
—
0
Max.
85
65
—
—
—
—
30
30
30
35
25
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been clocked.
2. Transition is measured ±500mV from steady state voltage.
3. Guaranteed by design, not production tested.
4. Minimum propagation delay times are guaranteed, not production tested.
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