电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

7205L50TPG8

产品描述FIFO
产品类别存储   
文件大小256KB,共15页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 全文预览

7205L50TPG8概述

FIFO

7205L50TPG8规格参数

参数名称属性值
厂商名称IDT (Integrated Device Technology)
包装说明,
Reach Compliance Codecompliant
Is SamacsysN
Base Number Matches1

文档预览

下载PDF文档
CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9
8,192 x 9, 16,384 x 9
32,768 x 9 and 65,536 x 9
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
IDT7203
IDT7204
IDT7205
IDT7206
IDT7207
IDT7208
FEATURES:
First-In/First-Out Dual-Port memory
2,048 x 9 organization (IDT7203)
4,096 x 9 organization (IDT7204)
8,192 x 9 organization (IDT7205)
16,384 x 9 organization (IDT7206)
32,768 x 9 organization (IDT7207)
65,636 x 9 organization (IDT7208)
High-speed: 12ns access time
Low power consumption
— Active: 660mW (max.)
— Power-down: 44mW (max.)
Asynchronous and simultaneous read and write
Fully expandable in both word depth and width
720x family is pin and functionally compatible from 256 x 9 to 64k x 9
Status Flags: Empty, Half-Full, Full
Retransmit capability
High-performance CMOS technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing for #5962-88669 (IDT7203), 5962-89567
(IDT7203), and 5962-89568 (IDT7204) are listed on this function
Industrial temperature range (–40°C to +85°C) is available
(plastic packages only)
Green parts available, see ordering information
DESCRIPTION:
The IDT7203/7204/7205/7206/7207/7208 are dual-port memory buffers
with internal pointers that load and empty data on a first-in/first-out basis. The
device uses Full and Empty flags to prevent data overflow and underflow and
expansion logic to allow for unlimited expansion capability in both word size and
depth.
Data is toggled in and out of the device through the use of the Write (W) and
Read (R) pins.
The device's 9-bit width provides a bit for a control or parity at the user’s
option. It also features a Retransmit (RT) capability that allows the read pointer
to be reset to its initial position when
RT
is pulsed LOW. A Half-Full Flag is
available in the single device and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They
are designed for applications requiring asynchronous and simultaneous read/
writes in multiprocessing, rate buffering and other applications.
Military grade product is manufactured in compliance with MIL-STD-883,
Class B.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D
0
-D
8
)
W
WRITE
CONTROL
WRITE
POINTER
RAM ARRAY
2,048 x 9
4,096 x 9
8,192 x 9
16,384 x 9
32,768 x 9
65,536 x 9
READ
POINTER
THREE-
STATE
BUFFERS
R
READ
CONTROL
FLAG
LOGIC
DATA OUTPUTS
(Q
0
-Q
8
)
RS
RESET
LOGIC
FL/RT
EF
FF
XI
EXPANSION
LOGIC
XO/HF
2661 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL, MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
©
2017 Integrated Device Technology, Inc. All rights reserved. Product subject to change without notice.
NOVEMBER 2017
DSC-2661/19
基于FPGA的矩阵键盘控制
周立功老师的文档 本帖最后由 白丁 于 2013-7-18 17:52 编辑 ]...
白丁 FPGA/CPLD
两种石英晶体振荡电路的振荡频率不为晶体的频率,为什么?
如图:为两种石英晶体振荡电路,可仿真的结果无论晶体设置为多大的频率,其输出的信号周期都为40us左右 按照书上的网络资料显示:该电路可以输出几兆到几十兆的信号,仅与石英晶体的谐振频率有 ......
唯美阿德 模拟电子
买HP电脑时附送的计步器
计步控制按钮 36022 FM控制按钮 36023 显示时间 36024 秒表功能 36025...
leslie 创意市集
通过FPGA控制两组16位数据的切换输出
两组16位的数据,当其中一组发生变化时,输出就发生变化。...
wsshine FPGA/CPLD
请教一个有关EVC开发程序在PDA上运行的问题。
在EVC中做好的小程序,把它复制然后粘贴到wince开发平台上,不可以运行呀?在虚拟模拟器上是可以运行的。...
aixia 嵌入式系统
是德科技最近与新加坡南洋理工大学合作开发混动汽车车联网通信技术,预测前景不错
2020年12月3日,是德科技公司(NYSE:KEYS)宣布与新加坡南洋理工大学(NTU)合作开发用于混动汽车车联网(V2X)通信系统的收发信机测试台。是德科技是一家电子测试和测量领先的技术公司,致力 ......
小舞和唐三 求职招聘

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2122  1629  1556  2166  2884  5  48  36  35  41 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved