74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
Rev. 05 — 21 March 2006
Product data sheet
1. General description
The 74LVT16244B; 74LVTH16244B is a high-performance BiCMOS product designed for
V
CC
operation at 3.3 V.
This device is a 16-bit buffer and line driver featuring non-inverting 3-state bus outputs.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
2. Features
I
I
I
I
I
I
I
I
I
I
16-bit bus interface
3-state buffers
Output capability: +64 mA and
−32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Power-up 3-state
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Latch-up protection:
N
JESD78: exceeds 500 mA
I
ESD protection:
N
MIL STD 833 method 3015: exceeds 2000 V
N
Machine model: exceeds 200 V
3. Quick reference data
Table 1.
Quick reference data
GND = 0 V; T
amb
= 25
°
C.
Symbol Parameter
t
PLH
t
PHL
C
i
C
o
I
CC
LOW-to-HIGH propagation
delay nAn to nYn
Conditions
C
L
= 50 pF; V
CC
= 3.3 V
Min
-
-
-
-
-
Typ
1.8
1.7
3
9
70
Max
-
-
-
-
-
Unit
ns
ns
pF
pF
µA
HIGH-to-LOW propagation C
L
= 50 pF; V
CC
= 3.3 V
delay nAn to nYn
input capacitance
output capacitance
quiescent supply current
V
I
= 0 V or 3.0 V
outputs disabled;
V
O
= 0 V or 3.0 V
outputs disabled;
V
CC
= 3.6 V; I
O
= 0 A;
V
I
= GND or V
CC
Philips Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
4. Ordering information
Table 2.
Ordering information
Package
Temperature range Name
74LVT16244BDL
74LVT16244BDGG
74LVT16244BEV
74LVTH16244BDL
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
SSOP48
TSSOP48
VFBGA56
SSOP48
TSSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package; 48 leads;
body width 6.1 mm
plastic very thin fine-pitch ball grid array package;
56 balls; body 4.5
×
7
×
0.65 mm
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package; 48 leads;
body width 6.1 mm
Version
SOT370-1
SOT362-1
SOT702-1
SOT370-1
SOT362-1
Type number
74LVTH16244BDGG
−40 °C
to +85
°C
5. Functional diagram
1
1OE
48
2OE
25
3OE
24
4OE
1A0
1A1
17
1A2
1A3
1
1OE
25
2Y0
3OE
2A0
2A1
41
40
2A0
8
9
30
29
4A0
4Y0
19
20
2A2
2A3
2A1
2Y1
4A1
4Y1
3A0
3A1
38
2A2
2Y2
11
27
4A2
4Y2
22
3A2
3A3
4A0
23
4A1
4A2
4A3
001aae506
47
46
1A0
1Y0
2
3
36
35
3A0
3Y0
13
14
1A1
1Y1
3A1
3Y1
EN1
EN2
EN3
EN4
1
1
2
3
5
6
1
2
8
9
11
12
1
3
13
14
16
17
1
4
19
20
22
23
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
44
1A2
1Y2
5
33
3A2
3Y2
16
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
43
1A3
1Y3
6
32
3A3
3Y3
37
2A3
2OE
2Y3
12
26
4A3
4OE
4Y3
48
24
001aae231
Pin numbers are shown for SSOP and TSSOP
packages only.
Pin numbers are shown for SSOP and TSSOP
packages only.
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVT_LVTH16244B_5
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 05 — 21 March 2006
2 of 16
Philips Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
6. Pinning information
6.1 Pinning
74LVT16244B
74LVTH16244B
1OE
1Y0
1Y1
GND
1Y2
1Y3
V
CC
2Y0
2Y1
1
2
3
4
5
6
7
8
9
48 2OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 V
CC
41 2A0
40 2A1
39 GND
38 2A2
37 2A3
36 3A0
35 3A1
34 GND
33 3A2
32 3A3
31 V
CC
30 4A0
29 4A1
28 GND
27 4A2
26 4A3
25 3OE
001aae507
74LVT16244B
1
A
1OE
2
n.c.
3
n.c.
4
n.c.
5
n.c.
6
2OE
B
1Y1
1Y0
GND
GND
1A0
1A1
C
1Y3
1Y2
V
CC
GND
V
CC
GND
1A2
1A3
D
2Y1
2Y0
2A0
2A1
GND 10
2Y2 11
2Y3 12
3Y0 13
3Y1 14
GND 15
3Y2 16
3Y3 17
V
CC
18
4Y0 19
4Y1 20
GND 21
4Y2 22
4Y3 23
4OE 24
E
2Y3
2Y2
2A2
2A3
F
3Y0
3Y1
3A1
3A0
G
3Y2
3Y3
GND
GND
3A3
3A2
H
4Y0
4Y1
V
CC
GND
V
CC
GND
4A1
4A0
J
4Y2
4Y3
4A3
4A2
K
4OE
n.c.
n.c.
n.c.
n.c.
3OE
001aae508
Transparent top view
Fig 3. Pin configuration for SSOP48 and TSSOP48
Fig 4. Pin configuration for VFBGA56
6.2 Pin description
Table 3.
Symbol
1OE
n.c.
1Y0
1Y1
GND
1Y2
1Y3
V
CC
2Y0
74LVT_LVTH16244B_5
Pin description
Pin
(T)SSOP48
1
-
2
3
4
5
6
7
8
VFBGA56
A1
B2
B1
B3
C2
C1
C3
D2
output enable input 1OE
data output 1Y0
data output 1Y1
ground (0 V)
data output 1Y2
data output 1Y3
supply voltage
data output 2Y0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Description
A2, A3, A4, A5 not connected
Product data sheet
Rev. 05 — 21 March 2006
3 of 16
Philips Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
Pin description
…continued
Pin
(T)SSOP48
VFBGA56
D1
D3
E2
E1
F1
F2
G3
G1
G2
H3
H1
H2
J3
J1
J2
K1
K6
J5
J6
J4
H5
H6
H4
G5
G6
G4
F5
F6
E6
E5
D4
D6
D5
C4
C6
C5
B4
data output 2Y1
ground (0 V)
data output 2Y2
data output 2Y3
data output 3Y0
data output 3Y1
ground (0 V)
data output 3Y2
data output 3Y3
supply voltage
data output 4Y0
data output 4Y1
ground (0 V)
data output 4Y2
data output 4Y3
output enable input 4OE
output enable input 3OE
data input 4A3
data input 4A2
ground (0 V)
data input 4A1
data input 4A0
supply voltage
data input 3A3
data input 3A2
ground (0 V)
data input 3A1
data input 3A0
data input 2A3
data input 2A2
ground (0 V)
data input 2A1
data input 2A0
supply voltage
data input 1A3
data input 1A2
ground (0 V)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
-
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Description
Table 3.
Symbol
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
3Y2
3Y3
V
CC
4Y0
4Y1
GND
4Y2
4Y3
4OE
n.c.
3OE
4A3
4A2
GND
4A1
4A0
V
CC
3A3
3A2
GND
3A1
3A0
2A3
2A2
GND
2A1
2A0
V
CC
1A3
1A2
GND
K2, K3, K4, K5 not connected
74LVT_LVTH16244B_5
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 05 — 21 March 2006
4 of 16
Philips Semiconductors
74LVT16244B; 74LVTH16244B
3.3 V 16-bit buffer/driver; 3-state
Pin description
…continued
Pin
(T)SSOP48
VFBGA56
B6
B5
A6
data input 1A1
data input 1A0
output enable input 2OE
46
47
48
Description
Table 3.
Symbol
1A1
1A0
2OE
7. Functional description
7.1 Function table
Table 4.
Control
nOE
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
Function table
[1]
Input
nAn
L
H
X
Output
nYn
L
H
Z
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
Conditions
[1]
Min
−0.5
−0.5
−0.5
-
-
-
-
−65
[2]
Max
+4.6
+7.0
+7.0
−50
−50
128
−64
+150
150
Unit
V
V
V
mA
mA
mA
mA
°C
°C
output in OFF-state or
HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[1]
-
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability.
74LVT_LVTH16244B_5
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 05 — 21 March 2006
5 of 16
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
