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71T75702S75PFI8

产品描述TQFP-100, Reel
产品类别存储   
文件大小616KB,共27页
制造商IDT (Integrated Device Technology)
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71T75702S75PFI8概述

TQFP-100, Reel

71T75702S75PFI8规格参数

参数名称属性值
Brand NameIntegrated Device Technology
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码TQFP
包装说明LQFP, QFP100,.63X.87
针数100
制造商包装代码PK100
Reach Compliance Codenot_compliant
ECCN代码3A991.B.2.A
最长访问时间7.5 ns
其他特性FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)100 MHz
I/O 类型COMMON
JESD-30 代码R-PQFP-G100
JESD-609代码e0
长度20 mm
内存密度18874368 bit
内存集成电路类型ZBT SRAM
内存宽度36
湿度敏感等级3
功能数量1
端子数量100
字数524288 words
字数代码512000
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织512KX36
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码LQFP
封装等效代码QFP100,.63X.87
封装形状RECTANGULAR
封装形式FLATPACK, LOW PROFILE
并行/串行PARALLEL
峰值回流温度(摄氏度)225
电源2.5 V
认证状态Not Qualified
座面最大高度1.6 mm
最大待机电流0.06 A
最小待机电流2.38 V
最大压摆率0.295 mA
最大供电电压 (Vsup)2.625 V
最小供电电压 (Vsup)2.375 V
标称供电电压 (Vsup)2.5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn85Pb15)
端子形式GULL WING
端子节距0.65 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度14 mm
Base Number Matches1

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512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
IDT71T75702
2.5V I/O, Burst Counter
OBSOLETE PART
Flow-Through Outputs
Features
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V (±5%) I/O Supply (V
DDQ
)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Description
The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBT
TM
, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle the associated data cycle occurs, be
it read or write.
Pin Description Summary
A
0
-A
19
Address Inputs
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
Chip Enables
Output Enable
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
T OR
R F
A D
P E
E D
T N
S
E E
L M IGN
O M S
S
B O DE
O EC
R EW
T N
O
N
Input
Synchronous
Input
Synchronous
Input
Asynchronous
Synchronous
Read/Write Signal
Clock Enable
Input
Input
Synchronous
Individual Byte Write Selects
Clock
Input
Synchronous
N/A
Input
Advance Burst Address/Load New Address
Input
Synchronous
Static
N/A
N/A
N/A
N/A
Asynchronous
Synchronous
Synchronous
Static
Static
Linear/Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input/Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
The IDT71T75702/902 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71T75702/902
to be suspended as long as necessary. All synchronous inputs are
ignored when
CEN
is high and the internal device registers will hold their
previous values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71T75702/902 have an on-chip burst counter. In the burst
mode, the IDT71T75702/902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO
input pin. The
LBO
pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71T75702/902 SRAMs utilize IDT’s high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
1
©2009 Integrated Device Technology, Inc.
FEBRUARY 2009
DSC-5319/09
5319 tbl 01
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