HIGH-SPEED
2K x 16 CMOS DUAL-PORT
STATIC RAMS
Integrated Device Technology, Inc.
IDT7133SA/LA
IDT7143SA/LA
FEATURES:
• High-speed access
— Military: 25/35/45/55/70/90ns (max.)
— Commercial: 20/25/35/45/55/70/90ns (max.)
• Low-power operation
— IDT7133/43SA
Active: 500 mW (typ.)
Standby: 5mW (typ.)
— IDT7133/43LA
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Versatile control for write: separate write control for
lower and upper byte of each port
• MASTER IDT7133 easily expands data bus width to 32
bits or more using SLAVE IDT7143
• On-chip port arbitration logic (IDT7133 only)
•
BUSY
output flag on IDT7133;
BUSY
input on IDT7143
• Fully asynchronous operation from either port
• Battery backup operation–2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in 68-pin ceramic PGA, 68-pin Flatpack, 68-pin
PLCC, and 100-pin TQFP
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static
RAMs. The IDT7133 is designed to be used as a stand-alone
16-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM
together with the IDT7143 “SLAVE” Dual-Port in 32-bit-or-
more word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 32-bit-or-wider memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asyn-
chronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE
,
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 500mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each port typically consuming 200µW for a 2V
battery.
The IDT7133/7143 devices have identical pinouts. Each is
packaged in a 68-pin ceramic PGA, a 68-pin flatpack, a 68-pin
PLCC, and a 100-pin TQFP. Military grade product is manu-
factured in compliance with the latest revision of MIL-STD-
883, Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and
reliability.
FUNCTIONAL BLOCK DIAGRAM
R/
W
LUB(2)
CE
L
R/
CE
R
W
RUB(2)
R/
W
LLB(2)
OE
L
R/
W
RLB(2)
OE
R
I/O
8L
- I/O
15L
I/O
0L
- I/O
7L
I/O
CONTROL
I/O
CONTROL
I/O
8R
- I/O
15R
I/O
0R
- I/O
7R
BUSY
L(1)
A
10L
A
0L
ADDRESS
DECODER
11
BUSY
R(1)
MEMORY
ARRAY
ADDRESS
DECODER
11
A
10R
A
0R
NOTES:
1. IDT7133 (MASTER): BUSY is
open drain output and requires
pull-up resistor of 270Ω.
IDT7143 (SLAVE): BUSY is
input.
2. "LB" designates "Lower Byte"
and "UB" designates "Upper
Byte" for the R/
W
signals.
CE
L
ARBITRATION
LOGIC
(IDT7133 ONLY)
CE
R
2746 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2746/6
6.14
1
IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
(1,2)
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
I/O
1L
I/O
0L
V
CC
R/
LUB
R/
LLB
9
8
7
6
5
4
3
2
1
INDEX
68 67 66 65 64 63 62 61
60
59
58
57
56
55
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
A
10L
A
9L
A
8L
A
7L
54
53
52
51
50
49
48
47
46
45
OE
L
W
W
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IDT7133/43
J68-1
&
F68-1
PLCC/FLATPACK
TOP VIEW(3)
BUSY
L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CE
L
CE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
BUSY
R
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
R/
RUB
R/
RLB
W
W
A
10R
A
9R
A
8R
A
7R
A
6R
OE
R
2746 drw 02
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
OE
L
W
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
2
73
3
72
4
71
5
70
6
69
7
68
8
67
9
IDT7133/43
66
10
PN100-1
65
11
64
12
100-PIN
63
13
TQFP
62
14
TOP VIEW(3)
61
15
60
16
59
17
58
18
57
19
56
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
55
54
53
52
51
50
CE
L
INDEX
R
/W
LUB
N/C
N/C
N/C
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
N/C
V
CC
R/
LLB
N/C
BUSY
L
GND
N/C
N/C
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
BUSY
R
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
OE
R
R/
RLB
GND
N/C
R
R/
RUB
N/C
N/C
N/C
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
W
CE
W
2746 drw 03
NOTES:
1. Both V
CC
pins must be connected to the supply to ensure reliable operation.
2. Both GND pins must be connected to the supply to ensure reliable operation.
3. This text does not indicate orientation of the actual part-marking.
6.14
2
IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D)
(1,2)
51
50
48
46
44
42
40
38
36
11
53
A
6L
52
A
5L
49
A
3L
47
A
1L
45
BUSY
L
43
CE
R
41
A
0R
39
A
2R
37
A
4R
35
34
10
55
A
8L
54
A
7L
A
4L
A
2L
A
0L
CE
L
BUSY
R
A
1R
A
3R
A
5R
32
A
6R
33
09
A
10L
57
A
9L
56
A
8R
30
A
7R
31
08
R/
59
W
LLB
OE
L
58
A
10R
28
A
9R
29
07
V
CC
61
R/
W
LUB
R/
IDT7133/43
GU68-1
PGA
TOP VIEW(3)
26
W
RLB
OE
R
27
60
06
I/O
1L
63
I/O
0L
62
GND
24
R/
W
RUB
25
05
I/O
3L
65
I/O
2L
64
I/O
14R
22
I/O
15R
23
04
I/O
5L
67
I/O
4L
66
I/O
12R
20
I/O
13R
21
03
I/O
7L
68
1
I/O
6L
3
5
7
9
11
13
15
I/O
10R
18
I/O
11R
19
02
I/O
8L
2
I/O
9L
I/O
11L
4
6
I/O
13L
8
I/O
15L
GND
10
I/O
1R
12
I/O
3R
14
I/O
5R
16
I/O
8R
17
I/O
9R
01
INDEX
A
I/O
10L
B
I/O
12L
C
I/O
14L
D
V
CC
E
I/O
0R
F
I/O
2R
G
I/O
4R
H
I/O
6R
J
I/O
7R
K
L
2746 drw 04
NOTES:
1. Both V
CC
pins must be connected to the supply to ensure reliable operation.
2. Both GND pins must be connected to the supply to ensure reliable operation.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port
Right Port
Names
Chip Enable
Upper Byte Read/Write Enable
Lower Byte Read/Write Enable
Output Enable
Address
Data Input/Output
Busy Flag
Power
Ground
2746 tbl 01
CE
L
R/
W
LUB
R/
W
LLB
OE
L
A
0L
– A
10L
I/O
0L
– I/O
15L
CE
R
R/
W
RUB
R/
W
RLB
OE
R
A
0R
– A
10R
I/O
0R
– I/O
15R
BUSY
L
V
CC
GND
BUSY
R
6.14
3
IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Commercial
Military
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power
Dissipation
DC Output
Current
0 to +70
–55 to +125
–55 to +125
2.0
50
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHZ) TQFP ONLY
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Input/Output
Capacitance
Conditions
(2)
Max.
V
IN
= 3dV
V
OUT
= 3dV
9
10
Unit
pF
pF
T
A
T
BIAS
T
STG
P
T
(3)
I
OUT
–55 to +125
–65 to +135
–65 to +150
2.0
50
°C
°C
°C
W
mA
NOTES:
2746 tbl 03
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Ambient
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2746 tbl 04
NOTES:
2746 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of V
TERM
> Vcc
+ 0.5V.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max. Unit
5.5
0
6.0
0.8
V
V
V
V
2746 tbl 05
NOTES:
1. V
IL
(min.) = -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(Either port, V
CC
= 5.0V
±
10%)
IDT7133SA
IDT7143SA
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage (I/O
0
-I/O
15
)
Open Drain Output Low Voltage
(
BUSY
)
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
Min.
—
—
—
—
2.4
Max.
10
10
0.4
0.5
—
IDT7133LA
IDT7143LA
Min.
—
—
—
—
2.4
Max.
5
5
0.4
0.5
—
Unit
µA
µA
V
V
V
2746 tbl 06
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OL
= 16mA
I
OH
= -4mA
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
6.14
4
IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(3)
(V
CC
= 5.0V
±
10%)
IDT7133X20
(1)
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports — TTL
Level Inputs)
I
SB2
Standby Current
(One Port — TTL
Level Inputs)
I
SB3
Full Standby Current
(Both Ports —
CMOS Level Inputs)
I
SB4
Full Standby Current
(One Port — All
CMOS Level Inputs)
Test
Condition
Version
S
L
COM’L. S
L
MIL.
S
L
MIL.
IDT7143X20
(1)
Max.
Typ.
(2)
–
–
250
230
–
–
25
25
–
–
140
120
–
–
1
0.2
–
–
140
120
–
–
310
280
–
–
80
70
–
–
200
180
–
–
15
5
–
–
190
170
IDT7133X25
IDT7143X25
Typ.
(2)
Max.
250
230
250
230
25
25
25
25
140
100
140
100
1
0.2
1
0.2
140
120
140
120
330
300
300
270
90
80
80
70
230
190
200
170
30
10
15
4
220
200
190
170
IDT7133X35
IDT7143X35
Typ.
(2)
Max.
240
220
240
210
25
25
25
25
120
100
120
100
1
0.2
1
0.2
120
100
120
100
325
295
295
250
75
65
70
60
200
180
180
160
30
10
15
4
190
170
170
150
mA
mA
mA
Unit
mA
CE
= V
IL
Outputs Open
f = f
MAX(4)
CE
L
and
CE
R =
V
IH
f = f
MAX(4)
I
SB1
mA
COM’L. S
L
CE
"A"
= V
IL
and
CE
"
B"
= V
IH(5)
,
f=
Active
Port Outputs Open
Both Ports
CE
L
&
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(5)
f
MAX(4)
,
MIL.
S
L
COM’L. S
L
MIL.
S
L
COM’L. S
L
MIL.
S
L
COM’L. S
L
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(6)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V
Active Port Outputs
Open, f = f
MAX(4)
NOTES:
2746 tbl 07
1. Commercial only, 0°C to +70°C temperature range.
2. V
CC
= 5V, T
A
= +25°C for Typ., and are not production tested. I
CCDC
= 180mA (Typ.)
3. "X" in part numbers indicates power rating (SA or LA).
4. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC,
and using “AC Test Conditions”
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.14
5
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