MVTX2604
Managed 24-Port 10/100M + 2-Port
10/100/1000M Layer-2 Ethernet Switch
Data Sheet
Features
•
Integrated Single-Chip 10/100/1000M Ethernet
Switch
• Twenty-four 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII or GPSI (7WS)
interface options per port
• Two 10/100/1000M auto-negotiating Gigabit
Ethernet (GE) ports with GMII, TBI, and MII
interface options per port
July 2006
Ordering Information
MVTX2604AG
MVTX2604AG2
553 Pin HSBGA
553 Pin HSBGA**
**Pb Free Tin/Silver/Copper
-40°C to 85°C
•
•
•
Supports IP Multicast with IGMP snooping
High performance packet classification and
switching at full-wire speed
CPU access supports the following interface
options:
• 8/16-bit ISA interface in managed mode
• Serial interface in unmanaged mode, with optional
I
2
C EEPROM support
•
Operates stand-alone or can be cascaded
• Stacking port supports hot swap in managed
configuration
• Stacking port supports 2G mode for inter-chip
communications
•
Supports two Frame Data Buffer (FDB) memory
domains
(2 MB or 4 MB)
with pipelined, sync-burst
SRAM at 100 MHz
• Applies centralized shared memory architecture
•
Packet Filtering and Port Security
• Static address filtering for source and/or destination
MAC
• Static MAC address not subject to aging
• Secure mode freezes MAC address learning, each
port may independently use this mode
•
L2 Switching
• MAC address self learning, up to 64K MAC
addresses
• Supports port-based and tagged-based VLAN (IEEE
802.1Q)
• Supports up to 255 VLANs and IP multicast groups
• VLAN tag insertion and stripping selectable on a per
port, per VLAN basis
• Supports spanning tree on per-system (IEEE
802.1D/w) or per-VLAN basis (IEEE 802.1s)
VLAN 1 MCT
•
•
Supports Ethernet multicasting and broadcasting
and flooding control
Supports per-system option to enable flow
control for best effort frames even on QoS-
enabled ports
VLAN 1 MCT
Frame Data Buffer A
SRAM (1M / 2M)
Frame Data Buffer B
SRAM (1M / 2M)
FDB Interface
LED
FCB
Frame Engine
Search
Engine
MCT
Link
24 x 10/100M
RMII
Ports 0 - 23
GMII/
PCS
Port
24
GMII/
PCS
Port
25
Management
Module
16-bit
Parallel /
Serial
Figure 1 - System Block Diagram
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Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MVTX2604
•
QoS Support
•
•
•
•
•
Data Sheet
4 transmission priorities for Fast Ethernet ports and 8 transmission classes for Gigabit ports
Per-queue weighted random early discard (WRED) with 2 drop precedence levels
Scheduling using delay bounded (DB), strict priority (SP), and Weighted Fair Queuing (WFQ) disciplines
User controlled WRED thresholds
Buffer management: per-class, shared, and per-port buffer reservations
Port-based priority: priority in a frame can be overwritten by the priority of port
VLAN Priority field in VLAN tagged frame (IEEE 802.1p)
DS/TOS field in IP packet
UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
•
Classification based on:
•
•
•
•
•
•
The drop precedence of the above classifications is programmable
Supports IEEE 802.3ad link aggregation
•
•
•
•
3 port trunking groups
one group for the 2 Gigabit ports
two groups for 10/100 ports, with up to 4 ports per group
Load sharing among trunked ports can be based on:
- Source and/or destination MAC address
•
- Source port (Gigabit ports only)
Port Mirroring
• supports 2 mirroring ports in managed mode
• supports a either a dedicated mirroring port or port 23 in unmanaged mode
•
•
•
•
•
•
•
Built-in MIB statistics counters
Full Duplex Ethernet IEEE 802.3x Flow Control
Backpressure flow control for Half Duplex ports
Full set of LED signals provided by a serial interface, or 6 LED signals dedicated to Gigabit port status only
(without serial interface)
Recognizes Simple Bandwidth Management (SBM) and Resource Reservation Protocol (RSVP) packets
and forwards to CPU
Built-in reset logic triggered by system malfunction
Built-in self test (BIST) for internal and external SRAM
2
Zarlink Semiconductor Inc.
MVTX2604
Description
Data Sheet
The MVTX2604 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip
provides 24 ports at 10/100 Mbps, 2 ports at 1000 Mbps and a CPU interface for managed and unmanaged switch
applications. The Gigabit ports can also support 10/100 M and 2 G modes.
The chip supports up to 64K MAC addresses and up to 255 tagged-based Virtual LANs (VLANs). The centralized
shared memory architecture permits a very high performance packet forwarding rate at full wire speed. The chip is
optimized to provide low-cost, high-performance workgroup switching.
Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate
bandwidth of 6.4 Gbps to support full wire speed on all ports simultaneously. In the 2G-mode configuration, two
ZBT-SRAM domains are needed.
With delay bounded, strict priority, and/or WFQ transmission scheduling and WRED dropping schemes, the
MVTX2604 provides powerful QoS functions for various multimedia and mission-critical applications. The chip
provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is
assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged
frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The MVTX2604 recognizes a total of
16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range).
The MVTX2604 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports,
and the other two groups to 10/100 ports, where each 10/100 group can contain up to 4 ports. Port trunking/load
sharing can be used to group ports between interlinked switches to increase the effective network bandwidth.
In half-duplex mode all ports support backpressure flow control to minimize the risk of losing data during long
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The MVTX2604 also supports a per-
system option to enable flow control for best effort frames, even on QoS-enabled ports.
The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface (TBI) for connection to
SERDES chips. The PCS can be bypassed to provide a GMII interface.
Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are
collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface.
SNMP Management frames can be received and transmitted via the CPU interface creating a complete network
management solution.
The MVTX2604 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are
capable of directly interfacing to LVTTL levels. The MVTX2604 is packaged in a 553-pin Ball Grid Array package.
3
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MVTX2604
Changes Summary
The following table captures the changes from the April 2006 issue.
Revision Date
July 2006
Summary of Changes
Data Sheet
Updated G3 "Gn_RXDV Input Setup Times" min. from 2 ns to 1.2 ns.
The April 2006 issue is the starting point for the change summary section.
Revision Date
April 2006
Summary of Changes
- Added Pb-free order code (MVTX2604AG2)
- Corrected TSTOUT6 boostrap description, and clarified only applicable in
"managed" mode
- Corrected ECR1Pn default value (should be 0xC0)
- Corrected PR100 default value (should be 0x35)
- Corrected SFCB default value (should be 0x46)
- Corrected CPU addresses for registers CPUQOSC1,2,3
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Table of Contents
1.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1.1 Encapsulated view in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1.2 Encapsulated view in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2 Ball – Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 Ball – Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4 Signal Mapping and Internal Pull Up/Down Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.1 Frame Data Buffer (FDB) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2 MAC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.1 RMII MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.1.1 GPSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.1.2 SCANLINK and SCANCOL interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.2 GMII MAC Module (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2.2.1 Physical Coding Sublayer (PCS) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2.2.2 TBI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2.3 CPU MAC Module (CMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2.4 PHY Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3 Management Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.5 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6 LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6.1 Port Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.6.2 LED Interface Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.7 Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.8 Timeout Reset Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.0 System Configuration (Stand-alone and Stacking) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1 Management and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 Managed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.1 Register Configuration, Frame Transmission, and Frame Reception . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.1.1 Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.1.2 Rx/Tx of Standard Ethernet Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2.1.3 Control Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3 Unmanaged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1 I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1.3 Data Direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.1.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 Stacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.0 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.0 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2 Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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