HIGH SPEED
4K X 8 DUAL-PORT
STATIC RAM
WITH SEMAPHORE
Features
◆
71342SA/LA
◆
◆
High-speed access
– Commercial: 20ns(max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT71342LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
Fully asynchronous operation from either port
◆
◆
◆
◆
◆
Full on-chip hardware support of semaphore signalling be-
tween ports
Battery backup operation—2V data retention (LA only)
TTL-compatible; single 5V (±10%) power supply
Available in plastic packages
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/W
L
CE
L
R/W
R
CE
R
OE
L
I/O
CONTROL
I/O
CONTROL
OE
R
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
MEMORY
ARRAY
SEMAPHORE
LOGIC
SEM
L
ADDRESS
DECODER
ADDRESS
DECODER
SEM
R
A
0L
- A
11L
A
0R
- A
11R
2721 drw 01
JULY 2019
1
©2019 Integrated Device Technology, Inc.
DSC 2621/16
71342LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Description
The IDT71342 is a high-speed 4K x 8 Dual-Port Static RAM with full
on-chip hardware support of semaphore signalling between the two
ports.
The IDT71342 provides two independent ports with separate
control, address, and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. To assist in
arbitrating between ports, a fully independent semaphore logic block
is provided. This block contains unassigned flags which can be
accessed by either side; however, only one side can control the flag at any
time. An automatic power down feature, controlled by
CE
and
SEM,
permits the on-chip circuitry of each port to enter a very low standby power
mode (both
CE
and
SEM
HIGH).
Fabricated using CMOS high-performance technology, this device
typically operates on only 700mW of power. Low-power (LA) versions
offer battery backup data retention capability, with each port typically
consuming 200µW from a 2V battery. The device is packaged in either a
64-pin TQFP or a 52-pin PLCC.
Pin Configurations
(1,2,3)
I/O
3L
I/O
2L
I/O
1L
I/O
0L
A
9L
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
N/C
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
20 19 18 17 16 15 14 13 12 11 10 9 8
7
21
6
22
5
23
24
25
26
27
28
29
30
31
71342
PLG52
(4)
52-PIn PLCC
Top View
5)
1
52
51
50
49
4
3
2
A
0L
OE
L
A
10L
A
11L
SEM
L
R/W
L
CE
L
V
CC
CE
R
R/W
R
SEM
R
A
11R
A
10R
48
32
47
33
34 35 36 37 38 39 40 41 42 43 44 45 46
I/O
7R
OE
R
N/C
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
2721 drw 02a
6.42
2
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
N/C
A
7L
A
8L
A
9L
N/C
I/O
0L
I/O
1L
I/O
2L
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PLG52 package body is approximately .79 in x .79 in x .17 in.
PNG64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
N/C
N/C
A
10R
A
11R
SEM
R
R/W
R
CE
R
N/C
V
CC
CE
L
R/W
L
SEM
L
A
11L
A
10L
N/C
N/C
48 47 46 4544 43 42 41 40 39 38 37 36 3534 33
32
49
31
50
30
51
29
52
28
53
27
54
71342
26
55
PNG64
(4)
25
56
24
64-Pin TQFP
57
Top View
(5)
23
58
22
59
21
60
20
61
19
62
18
63
17
64
1 2 3 4 5 6 7 8 9 1011 12 1314 15 16
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
N/C
A
7R
A
8R
A
9R
N/C
N/C
I/O
7R
I/O
6R
I/O
5R
I/O
4R
N/C
I/O
3R
I/O
2R
I/O
1R
I/O
0R
GND
N/C
N/C
I/O
7L
I/O
6L
I/O
5L
I/O
4L
N/C
I/O
3L
2721 drw 03a
71342LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
Power
Dissipation
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
Maximum Operating
Temperature and Supply Voltage
(1,2)
Grade
Commercial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
2721 tbl 03
T
BIAS
T
STG
P
T
I
OUT
-55 to +125
-65 to +150
1.5
50
o
C
C
Industrial
o
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
W
mA
2721 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10 ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc +10%.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2721 tbl 04
Capacitance
(1)
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2721 tbl 02
NOTES:
1. V
IL
(min.) > -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V and from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage
(V
CC
= 5V ± 10%)
71342SA
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 6mA
I
OL
= 8mA
V
OH
Output High Voltage
I
OH
= -4mA
Min.
___
___
___
___
71342LA
Min.
___
___
___
___
Max.
10
10
0.4
0.5
___
Max.
5
5
0.4
0.5
___
Unit
µA
µA
V
V
V
2721 tbl 05
2.4
2.4
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
3
6.42
71342LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
(V
CC
= 5.0V ± 10%)
71342X20
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE
= V
IL
,
Outputs Disabled
SEM
= Don't Care
f = f
MAX
(3)
CE
L
and
CE
R
= V
IH
SEM
L
=
SEM
R
> V
IH
f = f
MAX
(3)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
Typ.
(2)
170
170
____
____
71342X25
Com'l & Ind
Typ.
(2)
160
160
160
160
25
25
25
25
95
95
95
95
1.0
0.2
1.0
0.2
95
95
95
95
Max.
280
240
310
260
80
50
100
80
180
150
210
170
15
4.0
30
10
170
120
210
190
71342X35
Com'l Only
Typ.
(2)
150
150
150
150
25
25
25
25
85
85
85
85
1.0
0.2
1.0
0.2
85
85
85
85
Max.
260
200
300
250
75
45
75
55
170
140
200
160
15
4.0
30
10
150
110
190
130
2721 tbl 06a
Max.
280
240
____
____
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
25
25
____
____
80
80
____
____
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
Active Port Outputs Disabled,
f=f
MAX
(3)
105
105
____
____
180
150
____
____
mA
I
SB3
Full Standby Current (Both
Ports -
CMOS Level Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
SEM
L
=
SEM
R
> V
CC
- 0.2V
f = 0
(3)
One Port
CE
"A"
or
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
SEM
L
=
SEM
R
> V
CC
- 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3)
1.0
0.2
____
____
15
4.5
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
105
105
____
____
170
130
____
____
mA
71342X45
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE
= V
IL
,
Outputs Disabled
SEM
= Don't Care
f = f
MAX
(3)
CE
L
and
CE
R
= V
IH
SEM
L
=
SEM
R
> V
IH
f = f
MAX
(3)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
Typ.
(2)
140
140
____
____
71342X55
Com'l Only
Typ.
(2)
140
140
140
140
25
25
25
25
75
75
75
75
1.0
0.2
1.0
2.0
75
75
75
75
Max.
240
200
270
220
70
40
70
50
160
130
180
150
15
4.0
30
10
150
100
170
120
71342X70
Com'l Only
Typ.
(2)
140
140
____
____
Max.
240
200
____
____
Max.
240
200
____
____
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
25
25
____
____
70
40
____
____
25
25
____
____
70
40
____
____
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
Active Port Outputs Disabled,
f=f
MAX
(3)
75
75
____
____
160
130
____
____
75
75
____
____
160
130
____
____
mA
I
SB3
Full Standby Current (Both
Ports -
CMOS Level Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
SEM
L
=
SEM
R
> V
CC
- 0.2
V
f = 0
(3)
One Port
CE
"A"
or
CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
SEM
L
=
SEM
R
> V
CC
- 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3)
1.0
0.2
____
____
15
4.0
____
____
1.0
0.2
____
____
15
4.0
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
75
75
____
____
150
100
____
____
75
75
____
____
150
100
____
____
mA
NOTES:
1. 'X' in part number indicates power rating (SA or LA).
2. V
CC
= 5V, T
A
= +25°C for typical, and parameters are not production tested.
3. f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby I
SB3.
2721 tbl 06b
6.42
4
71342LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
Industrial and Commercial Temperature Ranges
Data Retention Characteristics
Symbol
V
DR
I
CCDR
t
CDR
(3)
t
R
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Dese lect to Data Retention Time
Operation Recovery Time
(LA Version Only) V
LC
= 0.2V, V
HC
= V
CC
- 0.2V
Test Condition
___
Min.
2.0
Typ.
(1)
Max.
___
Unit
V
µA
ns
ns
2721 tbl 07
V
CC
= 2V,
CE
> V
HC
SEM
> V
HC
V
IN
> V
HC
or < V
LC
COM'L. & IND.
___
100
___
___
1500
___
___
0
t
RC
(2)
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and are not production tested.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
t
CDR
CE
V
IH
V
DR
V
DR
>
2V
4.5V
t
R
V
IH
2721 drw 04
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1 and 2
2721 tbl 08
+5V
1250Ω
DATA
OUT
775Ω
30pF
2721 drw 05
,
+5V
1250Ω
DATA
OUT
775Ω
5pF *
,
2721 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, t
HZ
, t
WZ
, t
OW
)
*Including scope and jig
5
6.42
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