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IDT72P51767L6BBG: 产品描述FIFO, 128KX40, 3.6ns, Synchronous, CMOS, PBGA376, 23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376; 产品类别存储; 文件大小799KB，共88页; 制造商IDT (Integrated Device Technology); 标准

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IDT72P51767L6BBG概述

FIFO, 128KX40, 3.6ns, Synchronous, CMOS, PBGA376, 23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376

IDT72P51767L6BBG规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	BGA
包装说明	23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376
针数	376
Reach Compliance Code	compliant
ECCN代码	EAR99
最长访问时间	3.6 ns
最大时钟频率 (fCLK)	166 MHz
周期时间	6 ns
JESD-30 代码	S-PBGA-B376
JESD-609代码	e3
内存密度	5242880 bit
内存集成电路类型	OTHER FIFO
内存宽度	40
功能数量	1
端子数量	376
字数	131072 words
字数代码	128000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	128KX40
可输出	NO
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA376,22X22,40
封装形状	SQUARE
封装形式	GRID ARRAY
并行/串行	SERIAL
峰值回流温度（摄氏度）	260
电源	1.8 V
认证状态	Not Qualified
最大待机电流	0.12 A
最大压摆率	0.2 mA
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	MATTE TIN
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	30
Base Number Matches	1

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1.8V MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 40 BIT WIDE CONFIGURATION

5,242,880 bits

10,485,760 bits

IDT72P51767

IDT72P51777

•

FEATURES

•

Choose from among the following memory density options:

IDT72P51767



Total Available Memory = 5,242,880 bits

IDT72P51777



Total Available Memory = 10,485,760 bits

Configurable from 1 to 128 Queues

Multiple default configurations of symmetrical queues

Default multi-queue device configurations

– IDT72P51767: 512 x 40 x 128Q

– IDT72P51777: 1,024 x 40 x 128Q

Number of queues and queue sizes may be configured; at

master reset, though serial programming, (via the queue

address bus)

166 MHz High speed operation (6ns cycle time)

0.48ns access time

Independent Read and Write access per queue

Echo Read Clock available

Internal PLL

On-chip Output Impedance matching

•

User Selectable Bus Matching Options:

– x40 in to x40 out

– x20 in to x20 out

– x40 in to x20 out

– x20in to x40out

User selectable I/O: 1.5V HSTL or 1.8V eHSTL

100% Bus Utilization, Read and Write on every clock cycle

Selectable Back off one (BOI) or IDT standard mode of operation

Ability to operate on packet or word boundaries

Mark and Re-Write operation

Mark and Re-Read operation

Individual, Active queue flags (EF,

FF, PAE, PAF)

8 bit parallel flag status on both read and write ports

Direct or polled operation of flag status bus

Expansion of up to 256 queues

JTAG Functionality (Boundary Scan)

Available in a 376-pin BGA, 1mm pitch, 23mm x 23mm

HIGH Performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

Green parts available, seeing Ordering Information

FUNCTIONAL BLOCK DIAGRAM

10G DDR MULTI-QUEUE FLOW-CONTROL DEVICE

ECHO CLOCK

WADEN

FSTR

WRADD

READ CONTROL

Q127

RADEN

ESTR

RDADD

WRITE CONTROL

Q126

REN

RCLK

EREN

WEN

WCLK

Q125

x40 or x20

DATA IN

PAF

PAFn

Din

Qout

x40 or x20

DATA OUT

WRITE FLAGS

READ FLAGS

PAE

PAEn

6724 drw01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2006

JANUARY 2006

DSC-6724/1

IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Table of Contents

Features ......................................................................................................................................................................................................................... 1

Description ...................................................................................................................................................................................................................... 5

Pin configuration .............................................................................................................................................................................................................. 7

Detailed Description ......................................................................................................................................................................................................... 8

Pin Descriptions ............................................................................................................................................................................................................. 10

Pin number table ........................................................................................................................................................................................................... 15

Recommended DC operating conditions ........................................................................................................................................................................ 16

Absolute maximum ratings .............................................................................................................................................................................................. 16

DC electrical characteristics ............................................................................................................................................................................................ 17

AC electrical characteristics ............................................................................................................................................................................................ 19

Functional description .................................................................................................................................................................................................... 22

Serial Programming .............................................................................................................................................................................................. 24

Default Programming ............................................................................................................................................................................................ 27

Parallel Programming ........................................................................................................................................................................................... 27

Modes of operation ........................................................................................................................................................................................................ 29

Standard mode operation ..................................................................................................................................................................................... 29

IDT Standard mode vs. BOI mode ........................................................................................................................................................................ 29

PLL on vs PLL off modes ...................................................................................................................................................................................... 30

Read Queue Selection and Read Operation ......................................................................................................................................................... 33

Switching Queues on the Write Port ...................................................................................................................................................................... 34

Switching Queues on the Read Port ..................................................................................................................................................................... 44

Flag Description ............................................................................................................................................................................................................ 52

PAFn

Flag Bus Operation .................................................................................................................................................................................... 52

Full Flag Operation ............................................................................................................................................................................................... 52

Empty Flag Operation ........................................................................................................................................................................................... 52

Almost Full Flag .................................................................................................................................................................................................... 53

Almost Empty Flag ................................................................................................................................................................................................ 53

JTAG Interface ............................................................................................................................................................................................................... 83

JTAG AC electrical characteristics ................................................................................................................................................................................... 87

Ordering Information ...................................................................................................................................................................................................... 88

List of Tables

Table 1 — Summary of the differences between the 4M MQ and 10G MQ ........................................................................................................................ 9

Table 2 — DC and AC specifications (informative) ......................................................................................................................................................... 21

Table 3 — IDT to XGMII Interface Mapping Schema ..................................................................................................................................................... 21

Table 4 — Device programming mode comparison ........................................................................................................................................................ 22

Table 5 — Setting the queue programming mode during master reset ............................................................................................................................. 23

Table 6 — ID[2:0] and WRADD[7:5]/RDADD[7:5] Configuration .................................................................................................................................... 27

Table 7 — Parallel Programming Mode Queue Configuration Example(1) ...................................................................................................................... 28

Table 8 — Write Address Bus, WRADD[7:0] ................................................................................................................................................................... 32

Table 9 — Read Address Bus, RDADD[7:0] .................................................................................................................................................................. 33

Table 10 — Write Queue Switch Operation .................................................................................................................................................................... 35

Table 11 — Backup Usage when Re-entering a Queue ................................................................................................................................................. 43

Table 13 — Same Queue Switch ................................................................................................................................................................................... 45

Table 12 — Read Queue Switch Operation.................................................................................................................................................................... 45

Table 14 — Flag operation boundaries & Timing ........................................................................................................................................................... 55

Table 15 — Interface Data Rates ................................................................................................................................................................................... 57

Table 16 — Bus-Matching Configurations ...................................................................................................................................................................... 58

JANUARY 18, 2006

IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Figures

Figure 1. Multi-Queue Flow-Control Device Block Diagram ............................................................................................................................................. 6

Figure 2a. AC Test Load ................................................................................................................................................................................................ 18

Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 18

Figure 3. HSTL Termination for XGMII ........................................................................................................................................................................... 21

Figure 4. Reference Signals .......................................................................................................................................................................................... 22

Figure 5. Expansion for Unlimited Number of Multi-Queue Devices Example .................................................................................................................. 28

Figure 6. Device Programming Hierarchy ..................................................................................................................................................................... 29

Figure 7. DDR Read Operation with PLL ON ................................................................................................................................................................. 30

Figure 8. DDR Read Operation with PLL OFF ............................................................................................................................................................... 30

Figure 9. SDR Read Operation with PLL ON ................................................................................................................................................................. 31

Figure 10. SDR Read Operation with PLL OFF ............................................................................................................................................................. 31

Figure 11. Write Port Switching Queues Signal Sequence .............................................................................................................................................. 34

Figure 12. Switching Queues Bus Efficiency ................................................................................................................................................................... 34

Figure 13. Simultaneous Queue Switching ..................................................................................................................................................................... 35

Figure 14. Application: Reading words from the MQ using the EOP bit to end the read operation ..................................................................................... 36

Figure 15. Output Data during a Queue Switch (SDR w/o PLL)...................................................................................................................................... 37

Figure 16. Output Data during a Queue Switch (SDR w/ PLL) ....................................................................................................................................... 38

Figure 17. Output Data during a Queue Switch (DDR w/ PLL) ....................................................................................................................................... 39

Figure 18. Output Data during a Queue Switch (DDR w/o PLL) ..................................................................................................................................... 40

Figure 19. Output Data during two Queue Switches (DDR w/ PLL) ................................................................................................................................ 41

Figure 20. Output Data during two Queue Switches (DDR w/o PLL) .............................................................................................................................. 42

Figure 21. Read Port Switching Queues Signal Sequence ............................................................................................................................................. 44

Figure 22. Switching Queues Bus Efficiency ................................................................................................................................................................... 44

Figure 23. Simultaneous Queue Switching ..................................................................................................................................................................... 45

Figure 24. MARK and Re-Write Sequence .................................................................................................................................................................... 46

Figure 25. MARK and Re-Read Sequence ................................................................................................................................................................... 46

Figure 26. MARKing a Queue - Write Queue MARK ...................................................................................................................................................... 47

Figure 27. MARKing a Queue - Read Queue MARK ..................................................................................................................................................... 47

Figure 28. UN-MARKing a Queue - Write Queue UN-MARK ......................................................................................................................................... 48

Figure 29. UN-MARKing a Queue - Read Queue UN-MARK ........................................................................................................................................ 48

Figure 30. Leaving a MARK active on the Write Port ...................................................................................................................................................... 49

Figure 31. Leaving a MARK active on the Read Port ..................................................................................................................................................... 49

Figure 32. Inactivating a MARK on the Write Port Active ................................................................................................................................................. 50

Figure 33. Inactivating a MARK on the Read Port Active ................................................................................................................................................ 50

Figure 34. DDR Source Synchronous Center Aligned Clocking .................................................................................................................................... 57

Figure 35. SDR Edge Aligned Clocking ........................................................................................................................................................................ 57

Figure 36. Bus-Matching Byte Arrangement .................................................................................................................................................................. 59

Figure 37. Master Reset ................................................................................................................................................................................................ 60

Figure 38. Default Programming .................................................................................................................................................................................... 61

Figure 39. Write Address/Read Address Programming ................................................................................................................................................... 62

Figure 40. Serial Port Connection for Serial Programming .............................................................................................................................................. 63

Figure 41. Serial Programming (2 Device Expansion) ................................................................................................................................................... 64

Figure 42. SDR Write Queue Select, Write Operation and Full Flag Operation ................................................................................................................ 65

Figure 43. DDR Write Operation, Write Queue Select, Full Flag Operation ...................................................................................................................... 66

Figure 44. Write Queue Select, Mark and Rewrite .......................................................................................................................................................... 67

Figure 45. Full Flag Timing in Expansion Configuration .................................................................................................................................................. 68

Figure 46. SDR Read Queue Select, Read Operation (IDT mode) ................................................................................................................................ 69

Figure 47. DDR Read Operation, Read Queue Select,

PAE

Flag Operation ......................................................................................................... 70

Figure 48. Read Queue Select, Mark and Reread (IDT mode) ...................................................................................................................................... 71

Figure 49. Standard Mode Pointers on Queue Re-entry for DDR Read Operation ......................................................................................................... 72

Figure 50. BOI Mode Pointers on Queue Re-entry for DDR Read Operation ................................................................................................................. 72

Figure 51. Read Queue Selection with Read Operations (IDT mode) (SDR mode, PLL = OFF) ..................................................................................... 73

Figure 52. Read Queue Select, Read Operation and

Timing .................................................................................................................................... 74

Figure 53. Almost Full Flag Timing and Queue Switch .................................................................................................................................................... 75

Figure 54. Almost Full Flag Timing ................................................................................................................................................................................. 75

JANUARY 18, 2006

IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Figures (Continued)

Figure 55. Almost Empty Flag Timing ............................................................................................................................................................................. 76

Figure 56.

PAEn

- Direct Mode - Status Word Selection ................................................................................................................................................. 77

Figure 57.

PAFn

- Direct Mode - Status Word Selection ................................................................................................................................................. 77

Figure 58.

PAEn

- Direct Mode, Flag Operation ............................................................................................................................................................. 78

Figure 59.

PAFn

- Direct Mode, Flag Operation ............................................................................................................................................................. 79

Figure 60.

PAFn

Bus - Polled Mode .............................................................................................................................................................................. 80

Figure 61. Connecting two 10G MQ 128Q devices in Expansion Mode .......................................................................................................................... 81

Figure 62. Connecting THREE or more 10G MQ 128Q in Expansion Mode Using WADDR bit 7/RDADD bit 7 ............................................................... 82

Figure 63. Boundary Scan Architecture ......................................................................................................................................................................... 83

Figure 64. TAP Controller State Diagram ....................................................................................................................................................................... 84

Figure 65. Standard JTAG Timing .................................................................................................................................................................................. 87

JANUARY 18, 2006

IDT72P51767L6BBG相似产品对比

	IDT72P51767L6BBG	IDT72P51767L6BBGI	IDT72P51767L7-5BBGI	IDT72P51777L6BBG	IDT72P51777L6BBGI	IDT72P51777L7-5BBGI	IDT72P51777L7-5BBG	IDT72P51767L7-5BBG
描述	FIFO, 128KX40, 3.6ns, Synchronous, CMOS, PBGA376, 23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376	FIFO, 128KX40, 3.6ns, Asynchronous, CMOS, PBGA376	FIFO, 128KX40, 3.8ns, Synchronous, CMOS, PBGA376, 23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376	FIFO, 256KX40, 3.6ns, Synchronous, CMOS, PBGA376, 23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376	FIFO, 256KX40, 3.6ns, Asynchronous, CMOS, PBGA376	FIFO, 256KX40, 3.8ns, Synchronous, CMOS, PBGA376, 23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376	FIFO, 256KX40, 3.8ns, Synchronous, CMOS, PBGA376, 23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376	FIFO, 128KX40, 3.8ns, Synchronous, CMOS, PBGA376, 23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376
是否无铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
最长访问时间	3.6 ns	3.6 ns	3.8 ns	3.6 ns	3.6 ns	3.8 ns	3.8 ns	3.8 ns
最大时钟频率 (fCLK)	166 MHz	166 MHz	133 MHz	166 MHz	166 MHz	133 MHz	133 MHz	133 MHz
JESD-30 代码	S-PBGA-B376	S-PBGA-B376	S-PBGA-B376	S-PBGA-B376	S-PBGA-B376	S-PBGA-B376	S-PBGA-B376	S-PBGA-B376
JESD-609代码	e3	e3	e3	e3	e3	e3	e3	e3
内存密度	5242880 bit	5242880 bit	5242880 bit	10485760 bit	10485760 bit	10485760 bit	10485760 bit	5242880 bit
内存集成电路类型	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO
内存宽度	40	40	40	40	40	40	40	40
端子数量	376	376	376	376	376	376	376	376
字数	131072 words	131072 words	131072 words	262144 words	262144 words	262144 words	262144 words	131072 words
字数代码	128000	128000	128000	256000	256000	256000	256000	128000
工作模式	SYNCHRONOUS	ASYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	ASYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	85 °C	85 °C	70 °C	85 °C	85 °C	70 °C	70 °C
组织	128KX40	128KX40	128KX40	256KX40	256KX40	256KX40	256KX40	128KX40
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
封装等效代码	BGA376,22X22,40	BGA376,22X22,40	BGA376,22X22,40	BGA376,22X22,40	BGA376,22X22,40	BGA376,22X22,40	BGA376,22X22,40	BGA376,22X22,40
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
峰值回流温度（摄氏度）	260	260	260	260	260	260	260	260
电源	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
最大待机电流	0.12 A	0.12 A	0.12 A	0.12 A	0.12 A	0.12 A	0.12 A	0.12 A
最大压摆率	0.2 mA	0.2 mA	0.2 mA	0.2 mA	0.2 mA	0.2 mA	0.2 mA	0.2 mA
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
端子面层	MATTE TIN	MATTE TIN	MATTE TIN	MATTE TIN	MATTE TIN	MATTE TIN	MATTE TIN	MATTE TIN
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	30	30	30	30	30	30	30	30
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	BGA	-	BGA	BGA	-	BGA	BGA	BGA
包装说明	23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376	-	23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376	23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376	-	23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376	23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376	23 X 23 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-376
针数	376	-	376	376	-	376	376	376
周期时间	6 ns	-	7.5 ns	6 ns	-	7.5 ns	7.5 ns	7.5 ns
功能数量	1	-	1	1	-	1	1	1
可输出	NO	-	NO	NO	-	NO	NO	NO
并行/串行	SERIAL	-	SERIAL	SERIAL	-	SERIAL	SERIAL	SERIAL
最大供电电压 (Vsup)	1.9 V	-	1.9 V	1.9 V	-	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	-	1.7 V	1.7 V	-	1.7 V	1.7 V	1.7 V

IDT72P51767L6BBG

IDT72P51767L6BBG概述

IDT72P51767L6BBG规格参数

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