MX98905B
FEATURES
• Control
– Controller and integrated bus interface total solu-
tion for IEEE 802.3, 10BASE5, 10BASE2 and
10BASE-T
– Software-compatible with industry standard
Ethernet adapters:
* Novell®'s NE 2000
* Western Digital/SMC's (8003E, 8003EBT,
8013EBT)
– Selectable buffer memory size
– No external bus logic or drivers
– Integrated controller, MCC and transceiver
– Full IEEE 802.3 AUI interface
– Single 5V supply
– Software-compatible with DP8390, DP83901
and DP83902
– Efficient buffer management implementation
• MCC module (Manchester Code Converter, also
called ENDEC)
– 10 Mbit/s Manchester encoding/decoding
– Squelch on receive and collision pairs
• TPI module (10BASE-T) transceiver
– Transmitter and receiver functions
– Collision detect, heartbeat and jabber
– Selectable link integrity test or link disable
– Polarity detection/correction
• Provides more powerful functions than NS DP83905
– Supports 15 I/O bases instead of 7
– Direct ID PROM access through I/O port instead
of through remote DMA
– Auto configuration function-supported makes
jumperless more powerful
– Solution for multiple LAN cards I/O bases conflict
problem to make manufacture more efficient.
– Supports "write ID back to EEPROM" function
instead of just writing configuration back to
EEPROM to make manufacture more efficient.
– Modify current configurations without turning off
power
– Variety of EEPROM supported
GENERAL DESCRIPTION
The MX98905 is designed for easy implementation of
CSMA/CD local area networks, which include
Ethernet® (10BASE5), Thin Ethernet (10BASE2), and
Twisted-pair Ethernet (10BASE-T). The Media Ac-
cess Control (MAC) and Encode-Decode (ENDEC)
are provided with an AUI interface. The 10BASE-T
transceiver functions according to the IEEE 802.3
standards, and the MX98905 10BASE-T transceiver
operations in compliance with the IEEE standard.
The functional block of the MX98905 consists of the
integration of the entire bus interface for PC-AT®
(Industry Standard Architecture, ISA) bus-based sys-
tems, receiver, transmitter, collision, heartbeat,
loopback, jabber, and link integrity blocks. When
combined with equalization resistors, the transceiver
transmits or receives filters, and pulse transformers
provide physical interface from the ENDEC module of
the MX98905 and the twisted-pair medium.
When software and hardware are properly configured,
the MX98905 can be set to be compatible with either
the NE2000 or EtherCard PLUS16™. All bus drivers
and control logic are integrated inside the chip to
reduce LAN card cost and area.
Manchester encoding and decoding is made possible
through the integrated ENDEC by means of a differ-
ential transceiver and phase lock loop decoder at 10
Mbit/sec. Collision detect translator and diagnostic
loopback capability are included in this process.
Interfacing directly with the transceiver module, the
ENDEC module also provides a fully IEEE-compliant
AUI (Attachment Unit Interface) to connect with other
media transceivers.
The Media Access Control function, provided by the
Ethernet Network Control (ENC) module, effects an
efficient packet transmission and reception control
through unique dual DMA channels and an internal
FIFO. To lessen board cost and area overheads, bus
arbitration and memory control logic are integrated.
Designed for easy interface with other transceivers by
means of the AUI interface, the MX98905 provides a
thorough single chip solution for 10BASE-T IEEE
802.3 network.
Constraints of CMOS processing require that
isolation, whether capacitive or inductive, be used at
the AUI differential signal interface for 10BASE5 and
10BASE2 applications.
1
REV. 1.3, NOV 20 ,1995
P/N: PM0365
MX98905B
PIN DESCRIPTIONS
A. ISA BUS INTERFACE
SYMBOL
SA0-SA19
PIN TYPE
I
PIN NUMBER
94-97, 99-106,
108-115
DESCRIPTION
LATCHED ADDRESS BUS: Low-order bits of the system's 24-bit
address bus. These lines are enabled onto the bus when BALE is
high and latched when BALE is deasserted. The MX98905 uses
these bits to decode the boot PROM address and internal registers.
In shared memory mode, they are used to decode accesses to
memory of the MX98905.
UNLATCHED ADDRESS BUS: High-order 7 bits of the 24-bit system
address bus. These lines are valid on the falling edge of BALE. The
MX98905 uses these bits to decode shared memory address in
shared memory mode. The validity of M16L depends on these
signals only.
SYSTEM DATA BUS: 16-bit system data bus. Used to transfer data
between the system and the MX98905.
LA17-LA23
I
76-82
SD0-SD15
I/O
127, 128, 130,
131, 133, 134,
136, 137, 73, 72
70, 69, 67,
66, 64, 63
BALE
I
88
BUS ADDRESS LATCH ENABLE: Active-high signal. Used to latch
valid addresses from the current Bus Master on the falling edge of
BALE.
SYSTEM BUS HIGH ENABLE: Active-low. Indicates that the system
expects a transfer on the address on the bus is 16 bits wide.
16-BIT I/O TRANSFER: Active-low. In I/O mode this signal indicates
that the MX98905 is responding to a 16-bit I/O access by driving 16
bits of data on SD0-SD15.
16-BIT MEMORY TRANSFER: Active-low.
MEMORY WRITE STROBE: Active-low. System uses this signal to
write to the memory map of the MX98905.
MEMORY READ STROBE: Active-low. System uses this signal to
read from the memory map of the MX98905.
LOW MEMORY STROBES: Active-low. The MX98905 uses MRDL
and MWRL in 16-bit memory mode and will use SMRDL and SMRL in
memory mode when ATXT is low (8-bit mode). Note that SMRDL and
SMWRL are also used to access the BOOT PROM.
I/O WRITE STROBE: Active-low. Strobe from system to write to the
I/O Map of the MX98905.
I/O READ STROBE: Active-low. Strobe from system to read from the
I/O Map of the MX98905.
SBHEL
I
83
IO16L
O
84
M16L
MWRL
O
I
86
74
MRDL
I
75
SMRDL,
SMWRL
I
119, 120
IOWRL
I
118
IORDL
I
117
P/N: PM0365
4
REV. 1.3, NOV 20 ,1995
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