PRELIMINARY
MX98725
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
1. FEATURES
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A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
Fully comply to IEEE 802.3u specification
Operates over 100 meters of STP and category 5
UTP cable
Support full and half duplex operation in both 100
Base-TX and 10 Base-T mode
Fully comply to PCI spec. 2.1 with bus clock ranges
from 16MHz to 33MHz
Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.0
Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.0
Magic Packet TM mode to support Remote-Power
On and Remote-Wake-Up.
100/10 Base-T NWAY auto negotiation function
Large on chip FIFOs for both transmit and receive
operations without external local memory
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Bus master architecture with linked host buffers
delivers the most optimized performance
32-bit bus master DMA channel provides ultra low
CPU utilization
Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
Support up to 256K bytes boot ROM and FLASH
interface
Three levels of loopback diagnostic capability
Support a variety of flexible address filtering modes
with 16 CAM address and 512 bits hash
MicroWire interface to EEPROM for customer's IDs
and configuration data
Single +5.0V power supply, standard CMOS tech-
nology, 160 pin PQFP package
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( Magic Packet technology is a trademark of Advanced
Micro Device Corp.)
2. GENERAL DESCRIPTIONS
The MX98725, second generation of 100/10 Base-T
single chip MAC controller, is designed specifically to
meet future demand on Fast Ethernet networking sys-
tem. Different from MX98715/715a3, MX98725 addition-
ally supports ACPI, Remote-Wake-Up, Remote-Power-
On, and up to 256K Bytes Flash interface to enhance
product's added-on value.
The MX9725 controller is an IEEE802.3u compliant
single chip 32-bit full duplex, 10/100Mbps highly inte-
grated Fast Ethernet combo solution, designed to ad-
dress high performance local area networking (LAN)
system application requirements.
The bus master architecture delivers the performance
needed for today high speed and powerful processors
technology. In other words, the MX98725 not only keeps
CPU utilization low while maximizing data throughput,
but it also optimizes the PCI bandwidth providing the
highest PCI bandwidth utilization. To further reduce
ownership costs the MX98725 uses drivers that are
backward-compatible with the original MXIC MX98713
series controllers.
The MX98725 contains a PCI local bus glueless inter-
face, a Direct Memory Access (DMA) buffer manage-
ment unit, an IEEE802.3u-compliant Media Access Con-
troller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98725-based adapter allows a single
RJ-45 connector to link with the other IEEE802.3u-com-
pliant device completely without any need to set con-
figuration.
In MX98725, an innovative and proprietary design
"Adaptive Network Throughput Control" (ANTC) is built-
in to configure itself automatically by MXIC's driver based
on the PCI burst throughput of different PCs. With this
proprietary design, MX98725 can always optimize its
operating bandwidth, network data integrity and through-
put for different PCs.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
1
MX98725
MXIC MX98725 features Remore-Wake-Up capability
and is compliant with the Advanced Configuration and
Power Interface (ACPI). This support enables a wide
range of wake-up capabilities, including the ability to cus-
tomize which network packets the PC responds to, even
when it is in a low-power state. PCs and workstations
designed to take advantage of these capabilities can be
turned on remotely and serviced simultaneiously over
the network from one central server, helping organiza-
tions reduce their total cost of ownership of high-perfor-
mance business PCs. With its on-chip support for both
little and big endian byte alignment, this controller can
also address non-PC applications.
For diskless applications of networking, remotely boot-
ing up is a necessary process. To update or modify the
code is such a complex process that network venders
or owners must provide a new EPROM, replace the ex-
isting EPROM on the network adaptor and then reboot
the computer. Thanks to the development of Flash
memory, MX98725 successfully incorporated Flash in-
terface to provide remotely boot code update service
and that means network maintenance becomes effort-
less.
3. PIN CONFIGURATIONS
FCSB
FWEB
BPA8
BPA7
BPA6
BPA5
BPA4
BPA3
BPA2
BPA1(EEDI)
BPA0(EECK)
EECS
BPA16
BPA17
BPD0(EED)
BPD1
BPD2
BPD3
BPD4
BPD5
BPD6
BPD7
GND
GND
VDD
VDD
AD0
AD1
GND
AD2
AD3
VDD
VDD
AD4
AD5
GND
GND
AD6
AD7
GND
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
FOEB
BPA9
BPA10
BPA11
BPA12
VDD
VDD
GND
GND
BPA13
BPA14
BPA15
LED0
LED1
LED2
LED3
AVDD
AGND
ARDA
AVDD
CKREF
AGND
AGND
AVDD
AGND
AGND
AVDD
AVDD
RXIN
RXIP
AVDD
AVDD
AGND
AGND
AVDD
TXON
TXOP
AGND
AGND
CPK
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
MX98725
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
CBEB0
AD8
AD9
GND
GND
AD10
AD11
AD12
VDD
VDD
AD13
AD14
GND
GND
AD15
CBEB1
PAR
SERRB
PERRB
VDD
STOPB
DEVSELB
TRDYB
IRDYB
GND
GND
FRAMEB
CBEB2
AD16
AD17
GND
AD18
AD19
VDD
VDD
AD20
AD21
GND
AD22
AD23
P/N:PM0488
RTX2EQ
RTX
ADVV
AGND
AGND
AVDD
AGND
AVDD
AGND
RESERVED
LANEAKE
EXSTARTB
EN_PRO
PMEB
INTAB
RSTB
PCICLK
GNTB
REQB
AD31
AD30
GND
AD29
AD28
VDD
VDD
AD27
VDD
VDD
GND
GND
AD26
AD25
GND
GND
AD24
CBEB3
IDSEL
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
REV. 1.7, SEP. 15, 1998
2
MX98725
4. PIN DESCRIPTION ( 160 PIN PQFP )
( T/S : tri-state, S/T/S : sustended tri-state, I : input, O : output, O/D : open drain )
Pin Name
AD[31:0]
Type
T/S
Pin No.
20,21,23,24,
27,32,33,36,
41,37,38,42,
44,45,48,49,
51,52,66,69,
70,73,74,75,
78,79,82,83,
86,87,90,91,
93,94
37,53
65,80
160 Pin Function and Driver
PCI address/data bus: shared PCI address/data bus lines. Little or
big endian byte ordering are supported.
CBEB[3:0]
T/S
PCI command and byte enable bus: shared PCI bus command and
byte enable bus, during the address phase of the transaction, these
four bits provide the bus command. During the data phase, these four
bits provide the byte enable.
PCI FRAMEB signal: shared PCI cycle start signal, asserted to
indicate the beginning of a bus transaction. As long as FRAMEB is
asserted, data transfers continue.
PCI Target ready: issued by the target agent, a data phase is
completed on the rising edge of PCICLK when both IRDYB and
TRDYB are asserted.
PCI Master ready: indicates the bus master's ability to complete
the current data phase of the transaction. A data phase is completed on
any rising edge of PCICLK when both IRDYB and TRDYB are asserted.
PCI slave device select: asserted by the target of the current bus
access. When MX98725 is the initiator of current bus access, the target
must assert DEVSELB within 5 bus cycles, otherwise cycle is aborted.
PCI initialization device select: target specific device select signal for
configuration cycles issued by host.
PCI bus clock input: PCI bus clock range from 16MHz to 33MHz.
PCI bus reset: host system hardware reset.
PCI bus interrupt request signal: wired to INTAB line.
PCI bus system error signal: If an address parity error is detected and
CFCS bit 8 is enabled, SERRB and CFCS’s bit 30 will be asserted.
PCI bus data error signal: As a bus master, when a data parity error is
detected and CFCS bit 8 is enabled, CFCS bit 24 and CSR5 bit 13 will
be asserted. As a bus target, a data parity error will cause PERRB to be
asserted.
FRAMEB
S/T/S
54
TRDYB
S/T/S
58
IRDYB
S/T/S
57
DEVSELB
S/T/S
59
IDSEL
PCICLK
RSTB
INTAB
SERRB
PERRB
I
I
I
O/D
O/D
S/T/S
38
17
16
15
63
62
P/N:PM0488
REV. 1.7, SEP. 15, 1998
3
MX98725
Pin Name
PAR
STOPB
REQB
GNTB
PMEB
EXSTARTB
LANWAKE
EN_RPO
BPA1
(EEDI)
BPA0
(EECK)
BPA[17:0]
O
110
Type
T/S
S/T/S
T/S
I
O/D
O/D
O
I
O
Pin No.
64
60
19
18
14
12
11
13
111
160 Pin Function and Driver
PCI bus parity bit: shared PCI bus even parity bit for 32 bits AD bus and
CBE bus.
PCI Target requested transfer stop signal: as bus master, assertion of
STOPB cause MX98725 either to retry, disconnect, or abort.
PCI bus request signal: to initiate a bus master cycle request
PCI bus grant acknowledge signal: host asserts to inform MX98725
that access to the bus is granted
Power Management Event: asserts low when Magic Packet is received.
Start externel circuit signal: asserts low to enable system's power
supply when Magic Packet is detected. Normally tri-stated.
LAN wake up signal: asserts high to indicate a magic packet has been
detected in Magic Packet enable mode.
Enable On-Chip Power-On-Reset : normally unconnected.
Boot PROM address bit 1(EECS=0): together with BPA[17:0] to access
external boot PROM up to 256KB.
EEPROM data in(EECS=1): EEPROM serial data input pin.
Boot PROM address bit 0(EECS=0): together with BPA[17:0] to access
external boot PROM or FLASH up to 256KB.
EEPROM clock(EECS=1): EEPROM clock input pin
Boot PROM address lines:
O
BPD0
(EEDO)
BPD[7:0]
EECS
FWEB
FOEB
FCSB
RDA
RTX
RTX2EQ
CPK
RXIP
RXIN
T/S
107,108
110-118
123-125
130-132
106
T/S
O
O
O
O
O
O
O
I
I
I
99-106
109
119
121
120
139
2
1
160
150
149
Boot PROM data line 0(EECS=0): boot ROM or flash data line 0.
(EEPROM data out(EECS=1): EEPROM serial data out pin(during
reset initialization.)
Boot PROM data lines: boot ROM or FLASH data lines 7-0.
EEPROM chip select.
FLASH Write Enable
FLASH ROM Output Enable
FLASH Chip Select pin
Connecting an external resistor to ground. See application note.
Connecting an external resistor to ground. See application note.
Connecting an external resistor to ground. See application note.
Connecting an external capacitor. See application note.
Twisted pair receive differential input: Support both 10Base-T and
100 Base-TX differential receive input.
Twisted pair receive differential input: Support both 10Base-T and
100 Base-TX receive differential input
P/N:PM0488
REV. 1.7, SEP. 15, 1998
4
MX98725
Pin Name
TXOP
TXON
CKREF
LED0
Type
O
O
I
O
Pin No.
157
156
141
133
160 Pin Function and Driver
Twisted pair transmit differential output: Support both 10 Base-T and
100 Base-TX transmit differential output
Twisted pair transmit differential output: Support both 10 Base-T and
100 Base-TX transmit differential output
Reference clock: 25MHz oscillator clock input
Programmable LED pin 0:
CSR9.28=1 Set the LED as Link Speed (10/100) LED.
CSR9.28=0 Set the LED as Activity LED.
Default is Activity LED after reset.
Programmable LED pin 1:
CSR9.29=1 Set the LED as Link/Activity LED.
CSR9.29=0 Set the LED as Good Link LED.
Default is RX LED after reset.
Programmable LED pin 2:
CSR9.30=1 Set the LED as Collision LED.
CSR9.30=0 Set the LED as TX LED.
Default is TX LED after reset.
Programmable LED pin 3:
CSR9.31=1 Set the LED as Full/Half Duplex LED.
CSR9.31=0 Set the LED as RX LED.
Default is RX LED after reset.
Reserved pin.
Digital Power pins.
LED1
O
134
LED2
O
135
LED3
O
136
RESERVED I
VDD
I
GND
I
AVDD
I
AGND
I
10
25,26,28,29,
30,46,47,61,
71,72,88,89,
95,96,126,127
22,30,31,34,
Digital Ground pins.
35,39,40,43,
50,55,56,67,
68,76,77,81,
84,85,92,97,
98,128,129
3,6,8,137,
Analog Power pins.
140,144,147,
148,151,152,
155
4,5,7,9,138,
Analog Ground pins.
142,143,145,
146,153,154,
158,159
P/N:PM0488
REV. 1.7, SEP. 15, 1998
5
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