19-3837; Rev 0; 10/05
Precision Temperature Monitor for
DDR Memory Modules
General Description
The MAX6604 high-precision temperature sensor is
designed for thermal monitoring functions in DDR memo-
ry modules. The device is readable and programmable
through the 2-wire SMBus™/I
2
C-compatible interface.
Three address inputs set the bus address for the temper-
ature sensor to provide up to eight devices on one bus.
The internal thermal sensor continuously monitors the
temperature and updates the temperature data eight
times per second. The master can read the tempera-
ture data at any time. Since the thermal sensor is locat-
ed on the memory module, temperature data recorded
accurately represents the temperature of the compo-
nents on the module. Consequently, the MAX6604 pro-
vides a much more accurate measurement of module
temperature than techniques involving temperature
sensors on the motherboard. In addition, the device
responds more quickly to temperature changes on the
module than a motherboard sensor.
The MAX6604 also features an interrupt-output indica-
tor for temperature-threshold monitoring. The threshold
levels are programmable through the digital interface.
The MAX6604 operates from -20°C to +125°C, and is
available in JEDEC-standard 8-pin TSSOP and TDFN
(MO-229-WCED-2) packages.
Features
♦
JEDEC Compliant
♦
±1°C Temperature-Monitoring Accuracy
♦
Overtemperature Interrupt with Programmable
Threshold
♦
+2.7V to +3.6V Operating Voltage Range
♦
SMBus/I
2
C-Compatible Interface
♦
300µA Typical Operating Current
♦
3µA Typical Shutdown Current
♦
-20°C to +125°C Operating Temperature Range
♦
8-Pin TSSOP and TDFN (MO-229-WCED-2)
Packages
MAX6604
Ordering Information
PART
MAX6604ATA
TEMP RANGE
-20°C to +125°C
PIN-PACKAGE
PKG
CODE
8 TDFN-EP**
T823-1
(MO229-WCED-2)
H8-1
MAX6604AHA -20°C to +125°C 8 TSSOP
**EP
= Exposed paddle.
Applications
Memory Modules
Desktop Computers
Notebook Computers
Workstations
Networking Equipment
TOP VIEW
Pin Configurations
VCC
EVENT SCL
SDA
5
8
7
6
MAX6604
1
A0
2
A1
3
A2
4
GND
Typical Application Circuit appears at end of data sheet.
TDFN-EP**
A0
1
8
VCC
SMBus is a trademark of Intel Corporation.
A1
2
7
EVENT
MAX6604
A2
3
6
SCL
GND
4
5
SDA
TSSOP
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Precision Temperature Monitor for
DDR Memory Modules
MAX6604
ABSOLUTE MAXIMUM RATINGS
All Input and Output Voltages ..................................-0.3V to +6V
Continuous Power Dissipation (TA = +70°C)
8-Pin TDFN (derate 16.7mW/°C above +70°C) ......1333.3mW
8-Pin TSSOP (derate 8.1mW/°C above +70°C) ........646.7mW
ESD Protection (all pins, Human Body Model) ....................±2kV
Junction Temperature ......................................................+150°C
Operating Temperature Range .........................-20°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +3.6V, T
A
= -20°C to +125°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C.) (Note 1)
PARAMETER
Operating Supply Voltage Range
Temperature Resolution
+3V
≤
V
CC
≤
+3.6V, +75°C
≤
T
A
≤
+95°C
Temperature Accuracy
Power-On Reset (POR) Threshold
POR Threshold Hysteresis
Undervoltage-Lockout Threshold
Operating Current
Standby Current
Conversion Time
Conversion Rate
DIGITAL INTERFACE (Note 2)
Logic-Input High Voltage (SCL, SDA)
Logic-Input Low Voltage (SCL, SDA)
Logic-Input Hysteresis (SCL, SDA)
Leakage Current (EVENT, SCL, SDA,
A2, A1, A0)
Logic-Output Low Voltage
(SDA, EVENT)
Logic-Output Low Sink Current
(SDA, EVENT)
Input Capacitance (SCL, SDA)
Serial-Clock Frequency
I
LEAK
V
OL
I
OL
C
IN
f
SCL
10
V
IN
= GND or V
CC
I
PULL_UP
= 350µA
V
OL
= 0.6V
6
5
100
-1
V
IH
V
IL
500
+1
50
2.1
0.8
V
V
mV
µA
mV
mA
pF
kHz
t
CONV
f
CONV
8
During conversion
+3V
≤
V
CC
≤
+3.6V, +40°C
≤
T
A
≤
+125°C
+3V
≤
V
CC
≤
+3.6V, -20°C
≤
T
A
≤
+125°C
V
CC
falling edge
-1
-2
-3
2.0
90
2.4
0.3
3
0.5
6
125
SYMBOL
V
CC
CONDITIONS
MIN
+2.7
0.125
11
+1
+2
+3
V
mV
V
mA
µA
ms
Hz
°C
TYP
MAX
+3.6
UNITS
V
°C
bits
2
_______________________________________________________________________________________
Precision Temperature Monitor for
DDR Memory Modules
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.7V to +3.6V, T
A
= -20°C to +125°C, unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C.) (Note 1)
PARAMETER
Bus Free Time Between STOP and
START Condition
Repeat START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
Clock High Period
Data Hold Time
Data Setup Time
Receive SCL/SDA Rise Time
Receive SCL/SDA Fall Time
Pulse Width of Spike Suppressed
SYMBOL
t
BUF
t
SU:STA
t
HD:STA
t
SU:STO
t
LOW
t
HIGH
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SP
0
90% of SMBDATA to 10% of SMBCLK
90% to 90%
10% of SMBDATA to 90% of SMBCLK
90% of SMBCLK to 10% of SMBDATA
10% to 10%
90% to 90%
CONDITIONS
MIN
4.7
4.7
4
4
4.7
4
300
250
1000
300
50
TYP
MAX
UNITS
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
MAX6604
Note 1:
All parameters are tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2:
Guaranteed by design.
_______________________________________________________________________________________
3
Precision Temperature Monitor for
DDR Memory Modules
MAX6604
Typical Operating Characteristics
(Typical values are at V
CC
= +3.3V, T
A
= +25°C.)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX6604 toc01
SUPPLY CURRENT
vs. TEMPERATURE
MAX6604 toc02
TEMPERATURE ERROR
vs. TEMPERATURE
MAX6604 toc03
6
SHUTDOWN SUPPLY CURRENT (µA)
5
4
3
V
CC
= 3.0V
2
1
0
-50
0
50
TEMPERATURE (°C)
100
V
CC
= 2.7V
V
CC
= 3.6V
V
CC
= 3.3V
360
V
CC
= 3.3V
340
SUPPLY CURRENT (µA)
V
CC
= 3.6V
3
2
TEMPERATURE ERROR (°C)
1
0
-1
V
CC
= 3.6V
-2
-3
V
CC
= 3.3V
V
CC
= 3.0V
320
300
280
V
CC
= 2.7V
260
150
-50
0
V
CC
= 3.0V
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
150
TEMPERATURE ERROR
vs. POWER SUPPLY NOISE FREQUENCY
SQUARE WAVE APPLIED
TO V
CC
WITH NO BYPASS
CAPACITOR
200mV
PP
1.5
MAX6604 toc04
2.5
TEMPERATURE ERROR (°C)
2.0
1.0
20mV
PP
0.5
0
0.1
10
1,000
100,000
POWER SUPPLY NOISE FREQUENCY (kHz)
Pin Description
PIN
1
2
3
4
5
6
7
8
NAME
A0
A1
A2
GND
SDA
SCL
EVENT
V
CC
FUNCTION
Address Input. Must connect to GND or V
CC
to set value.
Address Input. Must connect to GND or V
CC
to set value.
Address Input. Must connect to GND or V
CC
to set value.
Ground
Serial-Data Input/Output. Open drain. Connect to a pullup resistor.
Serial-Clock Input. Connect to a pullup resistor.
Event Output. Open drain. Connect to a pullup resistor.
Supply Voltage. Connect a 0.1µF capacitor to GND as close as possible to the device.
4
_______________________________________________________________________________________
Precision Temperature Monitor for
DDR Memory Modules
Detailed Description
The MAX6604 high-precision temperature sensor con-
tinuously monitors temperature and updates the
temperature data eight times per second. The device
functions as a slave on the SMBus/I
2
C-compatible inter-
face. The master can read the temperature data at any
time through the digital interface. The MAX6604 also
features an open-drain, event-output indicator for tem-
perature-threshold monitoring.
From a software perspective, the MAX6604 appears as a
set of 16-bit registers that contain temperature data,
alarm threshold values, and control bits. A standard
SMBus/I
2
C-compatible, 2-wire serial interface reads tem-
perature data and writes control bits and alarm threshold
data. Each device responds to its own SMBus/I
2
C slave
address, which is selected using A0, A1, and A2. See
the
Device Addressing
section for details.
The MAX6604 employs standard I
2
C/SMBus protocols
using 16-bit registers: write word and read word. Write
a word of data (16 bits) by first sending MAX6604’s I
2
C
address (0011-A2-A1-A0-0), then sending the 8-bit
command byte, followed by the first 8-bit data byte.
Note that the slave issues an acknowledge after each
byte is written. After the first 8-bit data byte is written,
the MAX6604 also returns an acknowledge. However,
the master does not generate a stop condition after the
first byte has been written. The master continues to
write the second byte of data with the slave acknowl-
edging. After the second byte has been written, the
master then generates a stop condition. See Figure 2.
To read a word of data, the master generates a new
start condition and sends MAX6604’s I
2
C address with
the R/W bit high (1010-A2-A1-A0-1), then sends the 8-
bit command byte. Again, the MAX6604 issues an ACK
for each byte received. The master again sends the
device address, following an acknowledge. Next, the
master reads the contents of the selected register,
beginning with the most significant bit, and acknowl-
edges if the most significant data byte is successfully
received. Finally, the master reads the least significant
data byte and issues a NACK, followed by a stop con-
dition to terminate the read cycle.
MAX6604
Serial Interface
SMBus/I
2
C
The MAX6604 is readable and programmable through
the SMBus/I
2
C-compatible interface. The device func-
tions as a slave on the interface. Figure 1 shows the
general timing diagram of the clock (SCL) and the data
(SDA) signals for the SMBus/I
2
C-compatible interface.
The SDA and SCL bus lines are at logic-high when the
bus is not in use. Pullup resistors from the bus lines to
the supply are required when push-pull circuitry is not
driving the lines. The data on the SDA line can change
only when the SCL line is low. Start and stop conditions
occur when SDA changes state while the SCL line is
high (Figure 1). Data on SDA must be stable for the
duration of the setup time (t
SU:DAT
) before SCL goes
high. Data on SDA is sampled when SCL toggles high
with data on SDA is stable for the duration of the hold
time (t
HD:DAT
). Note that a segment of data is transmit-
ted in an 8-bit byte. A total of nine clock cycles are
required to transfer a byte to the MAX6604. Since the
MAX6604 employs 16-bit registers, data is transmitted
or received in two 8-bit bytes (16 bits). The device
acknowledges the successful receipt for each byte by
pulling the SDA line low (issuing an ACK) during the
ninth clock cycle of each byte transfer.
SDA
t
BUF
t
SU:DAT
t
HD:DAT
t
SU:STA
t
HD:STA
t
SU:STO
SCL
t
LOW
t
HD:STA
t
R
t
F
START CONDITION
REPEATED START CONDITION
STOP CONDITION
Figure 1. SDA and SCL Timing Diagram
_______________________________________________________________________________________
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