HIGH-SPEED 2.5V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
Features
◆
◆
PRELIMINARY
IDT70T35/34L
IDT70T25/24L
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70T35/34L (IDT70T25/24L)
– Commercial: 20/25ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT70T35/34L (IDT70T25/24L)
Active: 200mW (typ.)
Standby: 600
µ
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70T35/34L (IDT70T25/24L) easily expands data bus
◆
◆
◆
◆
◆
◆
◆
◆
width to 36 bits (32 bits) or more using the Master/Slave
select when cascading more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 2.5V (±100mV) power supply
Available in a 100-pin Thin Quad Flatpack (TQFP) package
and 100-pin fine pitch Ball Grid Array (fpBGA)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
,
I/O
9L
-I/O
17L
(5)
I/O
0L
-I/O
8L
(4)
BUSY
L
(2,3)
I/O
9R
-I/O
17R
(5)
I/O
Control
I/O
Control
I/O
0R
-I/O
8R
(4)
BUSY
R
(2,3)
A
12R
(1)
A
0R
A
12L
(1)
A
0L
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
CE
L
OE
L
R/W
L
SEM
L
INT
L
(3)
NOTES:
1. A
12
is a NC for IDT70T34 and IDT70T24.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
4. I/O
0
x - I/O
7
x for IDT70T25/24.
5. I/O
8
x - I/O
15
x for IDT70T25/24.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(3)
5639 drw 01
M/S
DECEMBER 2002
1
DSC-5639/2
©2002 Integrated Device Technology, Inc.
IDT70T35/34L(IDT70T25/24L)
High-Speed 2.5V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Description
The IDT70T35/34L (IDT70T25/24L) is a high-speed 8/4K x 18
(8/4K x 16) Dual-Port Static RAM. The IDT70T35/34L (IDT70T25/24L)
is designed to be used as a stand-alone Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 36-bit (32-bit) or wider
memory system applications results in full-speed, error-free operation
without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 200mW of power.
The IDT70T35/34L (IDT70T25/24L) is packaged in a plastic 100-pin
Thin Quad Flatpack and a 100-pin fine pitch Ball Grid Array.
IDT70T35/34 Pin Configurations
(1,2,3,4)
12/06/02
Index
N/C
N/C
I/O
8L
I/O
17L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
Vss
I/O
15L
I/O
16L
V
DD
Vss
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
8R
I/O
17R
N/C
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
I/O
10L
I/O
9L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
Vss
I/O
1L
I/O
0L
OE
L
V
DD
R/W
L
SEM
L
CE
L
UB
L
LB
L
A
12L
(1)
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
IDT70T35/34PF
PN100-1
(5)
100-Pin TQFP
Top View
(6)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
Vss
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
,
5639 drw 02
NOTES:
1. A
12
is a NC for IDT70T34.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
I/O
7R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
Vss
I/O
16R
OE
R
R/W
R
Vss
SEM
R
CE
R
UB
R
LB
R
A
12R
(1)
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
6.42
2
IDT70T35/34L (IDT70T/25/24L)
High-Speed 2.5V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70T35/34 Pin Configurations(cont'd)
(1,2,3,4)
IDT70T35/34BF
BF100
(5)
100-Pin fpBGA
Top View
(6)
A2
A3
A4
A5
A6
A7
A8
A9
A10
12/06/02
A1
A
6R
B1
A
9R
B2
A
12R(1)
CE
R
B3
B4
V
SS
B5
V
SS
B6
V
SS
B7
I/O
13R
I/O
10R
I/O
7R
B8
B9
B10
NC
C1
NC
C2
A
8R
C3
A
10R
SEM
R
R/W
R
C4
C5
C6
OE
R
I/O
12R
I/O
9R
C7
C8
C9
I/O
6R
C10
A
3R
D1
A
4R
D2
A
5R
D3
A
7R
D4
UB
R
I/O
16R
I/O
15R
I/O
11R
I/O
8R
D5
D6
D7
D8
D9
I/O
3R
D10
A
1R
E1
INT
R
E2
A
2R
E3
NC
E4
A
11R
E5
LB
R
E6
I/O
14R
I/O
17R
I/O
5R
I/O
1R
E7
E8
E9
E10
M/S
BUSY
R
F1
F2
A
0R
F3
A
1L
F4
V
SS
F5
V
SS
F6
I/O
4R
F7
I/O
2R
F8
I/O
0R
F9
V
DD
F10
V
SS
G1
BUSY
L
G2
A
0L
G3
NC
G4
V
DD
G5
V
SS
G6
V
DD
G7
I/O
14L
I/O
15L
I/O
16L
G8
G9
G10
INT
L
H1
A
3L
H2
A
6L
H3
NC
H4
V
SS
H5
I/O
3L
H6
NC
H7
I/O
12L
H8
V
SS
H9
I/O
13L
H10
,
A
2L
J1
A
5L
J2
A
10L
J3
LB
L
J4
CE
L
J5
I/O
1L
J6
I/O
7L
J7
I/O
8L
J8
I/O
17L
I/O
11L
J9
J10
A
4L
K1
A
8L
K2
A
11L
K3
SEM
L
R/W
L
K4
K5
OE
L
K6
I/O
4L
K7
I/O
6L
K8
V
SS
K9
I/O
10L
K10
A
7L
A
9L
A
12L(1)
UB
L
V
DD
V
DD
I/O
0L
I/O
2L
I/O
5L
I/O
9L
5639 drw 03
NOTES:
1. A
12
is a NC for IDT70T34.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
3
IDT70T35/34L(IDT70T25/24L)
High-Speed 2.5V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70T25/24 Pin Configurations
(1,2,3,4)
12/06/02
Index
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
V
SS
I/O
14L
I/O
15L
V
DD
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
V
SS
I/O
1L
I/O
0L
OE
L
V
DD
R/W
L
SEM
L
CE
L
UB
L
LB
L
A
12L
(1)
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
IDT70T25/24PF
PN100-1
(5)
100-Pin TQFP
Top View
(6)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
5639 drw 04
.
NOTES:
1. A
12
is a NC for IDT70T24.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
V
SS
I/O
15R
OE
R
R/W
R
V
SS
SEM
R
CE
R
UB
R
LB
R
A
12R
(1)
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
6.42
4
IDT70T35/34L (IDT70T/25/24L)
High-Speed 2.5V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70T25/24 Pin Configurations(cont'd)
(1,2,3,4)
IDT70T25/24BF
BF100
(5)
100-Pin fpBGA
Top View
(6)
A2
A3
A4
A5
A6
A7
A8
A9
A10
12/06/02
A1
A
6R
B1
A
9R
B2
A
12R(1)
CE
R
B3
B4
V
SS
B5
V
SS
B6
V
SS
B7
I/O
12R
I/O
9R
I/O
7R
B8
B9
B10
NC
C1
NC
C2
A
8R
C3
A
10R
SEM
R
R/W
R
C4
C5
C6
OE
R
I/O
11R
I/O
8R
C7
C8
C9
I/O
6R
C10
A
3R
D1
A
4R
D2
A
5R
D3
A
7R
D4
UB
R
I/O
15R
I/O
14R
I/O
10R
D5
D6
D7
D8
NC
D9
I/O
3R
D10
A
1R
E1
INT
R
E2
A
2R
E3
NC
E4
A
11R
E5
LB
R
E6
I/O
13R
E7
NC
E8
I/O
5R
I/O
1R
E9
E10
M/S
BUSY
R
F1
F2
A
0R
F3
A
1L
F4
V
SS
F5
V
SS
F6
I/O
4R
F7
I/O
2R
F8
I/O
0R
F9
V
DD
F10
V
SS
G1
BUSY
L
G2
A
0L
G3
NC
G4
V
DD
G5
V
SS
G6
V
DD
G7
I/O
13L
I/O
14L
I/O
15L
G8
G9
G10
INT
L
H1
A
3L
H2
A
6L
H3
NC
H4
V
SS
H5
I/O
3L
H6
NC
H7
I/O
11L
H8
V
SS
H9
I/O
12L
H10
,
A
2L
J1
A
5L
J2
A
10L
J3
LB
L
J4
CE
L
J5
I/O
1L
J6
I/O
7L
J7
NC
J8
NC
J9
I/O
10L
J10
A
4L
K1
A
8L
K2
A
11L
K3
SEM
L
R/W
L
K4
K5
OE
L
K6
I/O
4L
K7
I/O
6L
K8
V
SS
K9
I/O
9L
K10
A
7L
A
9L
A
12L(1)
UB
L
V
DD
V
DD
I/O
0L
I/O
2L
I/O
5L
I/O
8L
5639 drw 05
NOTES:
1. A
12
is a NC for IDT70T24.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground.
4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
