74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge
trigger
Rev. 01 — 25 August 2006
Product data sheet
1. General description
The 74AUP1G74 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G74 provides the single positive-edge triggered D-type flip-flop with
individual data (D) input, clock (CP) input, set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
2. Features
s
Wide supply voltage range from 0.8 V to 3.6 V
s
High noise immunity
s
Complies with JEDEC standards:
x
JESD8-12 (0.8 V to 1.3 V)
x
JESD8-11 (0.9 V to 1.65 V)
x
JESD8-7 (1.2 V to 1.95 V)
x
JESD8-5 (1.8 V to 2.7 V)
x
JESD8-B (2.7 V to 3.6 V)
s
ESD protection:
x
HBM JESD22-A114-D Class 3A exceeds 5000 V
x
MM JESD22-A115-A exceeds 200 V
x
CDM JESD22-C101-C exceeds 1000 V
s
Low static power consumption; I
CC
= 0.9
µA
(maximum)
s
Latch-up performance exceeds 100 mA per JESD 78 Class II
s
Inputs accept voltages up to 3.6 V
s
Low noise overshoot and undershoot < 10 % of V
CC
Philips Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
s
I
OFF
circuitry provides partial Power-down mode operation
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP1G74DC
74AUP1G74GT
74AUP1G74GM
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
VSSOP8
XSON8
XQFN8
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
×
1.95
×
0.5 mm
plastic extremely thin quad flat package; no leads; 8
terminals; body 1.6
×
1.6
×
0.5 mm
SOT902-1
Type number
4. Marking
Table 2.
Marking
Marking code
p74
p74
p74
Type number
74AUP1G74DC
74AUP1G74GT
74AUP1G74GM
5. Functional diagram
7
SD
2
1
D
CP
SD
D
CP
FF
Q
RD
RD
6
mnb139
Q
Q
5
7
Q
3
1
2
6
S
C1
1D
R
mnb140
5
3
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74AUP1G74_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 25 August 2006
2 of 23
Philips Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Q
C
C
C
D
C
Q
C
RD
C
SD
001aae087
CP
C
C
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
74AUP1G74
CP
D
Q
GND
1
2
3
4
001aae322
8
7
6
5
V
CC
SD
RD
Q
Fig 4. Pin configuration SOT765-1 (VSSOP8)
74AUP1G74
74AUP1G74
CP
1
8
V
CC
terminal 1
index area
SD
1
V
CC
8
7
CP
D
2
7
SD
RD
2
6
D
Q
3
6
RD
Q
3
4
5
Q
GND
GND
4
5
Q
001aae324
001aae323
Transparent top view
Transparent top view
Fig 5. Pin configuration SOT833-1 (XSON8)
74AUP1G74_1
Fig 6. Pin configuration SOT902-1 (XQFN8)
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 25 August 2006
3 of 23
Philips Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
6.2 Pin description
Table 3.
Symbol
CP
D
Q
GND
Q
RD
SD
V
CC
Pin description
Pin
SOT765-1 and SOT833-1
1
2
3
4
5
6
7
8
SOT902-1
7
6
5
4
3
2
1
8
clock input (LOW-to-HIGH, edge triggered)
data input
complement flip-flop output
ground (0 V)
true flip-flop output
asynchronous reset-direct (active LOW)
asynchronous set-direct (active LOW)
supply voltage
Description
7. Functional description
Table 4.
Input
SD
L
H
L
Table 5.
Input
SD
H
H
[1]
Asynchronous operation
[1]
Output
RD
H
L
L
CP
X
X
X
D
X
X
X
Q
H
L
H
Q
L
H
H
Synchronous operation
[1]
Output
RD
H
H
CP
↑
↑
D
L
H
Q
n+1
L
H
Q
n+1
H
L
H = HIGH voltage level;
L = LOW voltage level;
↑
= LOW-to-HIGH CP transition;
X = don’t care.
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
74AUP1G74_1
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
Conditions
V
I
< 0 V
[1]
Min
−0.5
-
−0.5
-
[1]
Max
+4.6
−50
+4.6
−50
+4.6
±20
+50
Unit
V
mA
V
mA
V
mA
mA
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
−0.5
-
-
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 25 August 2006
4 of 23
Philips Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Table 6.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
I
GND
T
stg
P
tot
[1]
[2]
Parameter
ground current
storage temperature
total power dissipation
Conditions
Min
-
−65
Max
−50
+150
250
Unit
mA
°C
mW
T
amb
=
−40 °C
to +125
°C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110
°C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
−40
0
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
°C
ns/V
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
°C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−20 µA;
V
CC
= 0.8 V to 3.6 V
I
O
=
−1.1
mA; V
CC
= 1.1 V
I
O
=
−1.7
mA; V
CC
= 1.4 V
I
O
=
−1.9
mA; V
CC
= 1.65 V
I
O
=
−2.3
mA; V
CC
= 2.3 V
I
O
=
−3.1
mA; V
CC
= 2.3 V
I
O
=
−2.7
mA; V
CC
= 3.0 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
74AUP1G74_1
Conditions
Min
Typ
Max
-
-
-
-
Unit
V
V
V
V
0.70
×
V
CC
-
0.65
×
V
CC
-
1.6
2.0
-
-
-
-
V
CC
−
0.1
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
-
-
-
-
-
0.30
×
V
CC
V
0.35
×
V
CC
V
0.7
0.9
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
V
V
0.75
×
V
CC
-
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 25 August 2006
5 of 23
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
