CMOS Static RAM
64K (16K x 4-Bit)
Features
High-speed (equal access and cycle times)
– Military: 25/35/45/55/70/85ns (max.)
Low power consumption
Battery backup operation — 2V data retention
(L version only)
Available in high-density industry standard 22-pin, 300 mil
ceramic DIP
Produced with advanced CMOS technology
Inputs/outputs TTL-compatible
Military product compliant to MIL-STD-883, Class B
IDT7188S
IDT7188L
◆
◆
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◆
◆
◆
◆
Description
The IDT7188 is a 65,536-bit high-speed static RAM organized as
16K x 4. It is fabricated using IDT’s high-performance, high-reliability
technology — CMOS. This state-of-the-art technology, combined with
innovative circuit design techniques, provides a cost effective approach
for memory intensive applications.
Access times as fast as 25ns are available. The IDT7188 offers a
reduced power standby mode, I
SB1
, which is activated when
CS
goes
HIGH. This capability significantly decreases power while enhancing
system reliability. The low-power version (L) version also offers a battery
backup data retention capability where the circuit typically consumes only
30µW operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate from a single
5V supply. The IDT7188 is packaged in a 22-pin, 300 mil ceramic DIP
providing excellent board-level packing densities.
Military grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
Functional Block Diagram
A
0
V
CC
GND
65,536-BIT
MEMORY ARRAY
DECODER
A
13
I/O
0
I/O
1
I/O
2
I/O
3
COLUMN I/O
INPUT
DATA
CONTROL
,
CS
WE
2989 drw 01
FEBRUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-2989/09
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Pin Configuration
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CS
GND
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
Absolute Maximum Ratings
(1)
Symbol
Rating
Terminal Voltage with Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7.0
-55 to +125
-65 to +135
-65 to +150
1.0
50
Unit
V
o
o
D22-1
V
CC
A
13
A
12
A
11
A
10
A
9
I/O
3
I/O
2
I/O
1
I/O
0
WE
2989 drw 02
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
C
C
C
o
W
mA
2989 tbl 03
,
DIP
Top View
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
(T
A
= +25°C, f = 1.0MHz, V
CC
= 0V)
Symbol
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
6
Unit
pF
pF
2989 tbl 04
Capacitance
Pin Descriptions
Name
A
0
- A
13
CS
WE
I/O
0
- I/O
3
V
CC
GND
Description
Address Inputs
Chip Select
Write Enable
Data Input/Output
Power
Ground
2989 tbl 01
C
IN
C
I/O
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
0.8
Unit
V
V
V
V
2989 tbl 05
Truth Table
(1)
Mode
Standby
Read
Write
CS
H
L
L
WE
X
H
L
I/O
High-Z
D
OUT
D
IN
Power
Standby
Active
Active
2989 tbl 02
V
IH
V
IL
NOTE:
1. V
IL
(min.) = –3.0V for pulse width less than 20ns,once per cycle.
NOTE:
1. H = V
IH
, L = V
IL
, X = don't care.
Recommended Operating
Temperature and Supply Voltage
Grade
Military
Temperature
-55
O
C to +125
O
C
GND
0V
Vcc
5V ± 10%
2989 tbl 06
2
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
DC Electrical Characteristics
(V
CC
= 5.0V ± 10%)
IDT7188S
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
V
CC
= Max., V
IN =
GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 10mA, V
CC
= Min.
I
OL
= 8mA, V
CC
= Min.
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
Min.
____
IDT7188L
Min.
____
Max.
10
10
0.5
0.4
____
Max.
5
5
0.5
0.4
____
Unit
µA
µA
V
____
____
____
____
____
____
2.4
2.4
V
2989 tbl 07
DC Electrical Characteristics
(1)
Symbol
I
CC1
Parameter
Operating Power
Supply Current
CS
= V
IL
, Outputs Open
V
CC
= Max., f
=
0
(2)
Dynamic Operating Current
CS
= V
IL
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
Standby Power Supply
Current (TTL Level)
CS
> V
IH
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
Full Standby Power
Supply Current (CMOS Level)
CS
> V
HC
, V
CC
= Max., V
IN
> V
HC
or V
IN
< V
LC
, f = 0
(2)
Power
S
L
S
L
S
L
S
L
(V
CC
= 5V ± 10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
7188S25
7188L25
105
80
155
120
60
40
20
1.5
7188S35
7188L35
105
80
140
115
50
40
20
1.5
7188S45
7188L45
105
80
140
110
50
35
20
1.5
7188S55
7188L55
105
80
140
110
50
35
20
1.5
7188S70
7188L70
105
80
140
110
50
35
20
1.5
7188S85
7188L85
105
80
140
105
50
35
20
1.5
2989 tbl 08
Unit
mA
I
CC2
mA
I
SB
mA
I
SB1
mA
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
MAX
address and data inputs are cycling at the maximum frequency of read cycles of 1/t
RC
. f = 0 means no input lines change.
6.42
3
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Data Retention Characteristics
(L Version Only) (V
HC
= V
CC
- 0.2V)
Typ.
(1)
V
CC
@
Symbol
V
DR
I
CCDR
t
CDR
(3)
t
R
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Desele ct to Data Retention Time
Operation Recovery Time
Input Leakage Current
CS
> V
HC
V
IN
> V
HC
or
< V
LC
Test
Condition
____
Max.
V
CC
@
3.0V
____
Min.
2.0
____
2.0V
____
2.0V
____
3.0V
____
Unit
V
µA
ns
ns
µA
2989 tbl 09
10
____
15
____
600
____
900
____
0
t
RC
(2)
____
____
____
____
____
I
I
LI
I
(3)
____
____
2
2
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
Low V
CC
Data Retention Waveform
V
CC
t
CDR
CS
V
IH
DATA
RETENTION
MODE
4.5V
V
DR
≥
2V
V
DR
V
IH
2989 drw 03
4.5V
t
R
,
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2989 tbl 10
5V
480Ω
DATA
OUT
255Ω
30pF*
5V
480Ω
DATA
OUT
,
*Includes scope and jig capacitances
255Ω
5pF*
2989 drw 04
2989 drw 05
,
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
HZ
, t
LZ
, t
WZ
, t
OHZ
and t
OW
)
4
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
AC Electrical Characteristics
7188S25
7188L25
Symbol
Parameter
Min.
Max.
(V
CC
= 5.0V ± 10%)
7188S35
7188L35
Min.
Max.
7188S45
7188L45
Min.
Max.
7188S55
7188L55
Min.
Max.
7188S70
7188L70
Min.
Max.
7188S85
7188L85
Min.
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS
t
OH
t
LZ
(1)
t
HZ
(1)
t
PU
(1)
t
PD
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Output Select to Output in Low-Z
Chip Deselect to Output in High-Z
Chip Select to Power Up Time
Chip Deselect to Power Down Time
25
____
____
35
____
—
35
35
____
45
____
—
45
45
____
55
____
____
70
____
____
85
____
____
ns
ns
ns
ns
ns
ns
ns
ns
2989 tbl 11
25
25
____
55
55
____
70
70
____
85
85
____
____
____
____
____
____
____
5
5
____
5
5
____
5
5
____
5
5
____
5
5
____
5
5
____
____
____
____
____
____
____
10
____
14
____
14
____
20
____
25
____
30
____
0
____
0
____
0
____
0
____
0
____
0
____
25
35
45
55
70
85
NOTE:
1. This parameter is guaranteed by device characterization but is not production tested.
Timing Waveform of Read Cycle No. 1
(1,2)
t
RC (5)
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
2989 drw 06
,
Timing Waveform of Read Cycle No. 2
(1,3)
t
RC (5)
CS
t
ACS
t
LZ (4)
DATA
OUT
t
PU
I
CC
V
CC
SUPPLY
CURRENT I
SB
2989 drw 07
t
HZ (4)
DATA VALID
t
PD
HIGH IMPEDANCE
,
NOTES:
1.
WE
is HIGH for Read cycle.
2.
CS
is LOW for Read cycle.
3. Address valid prior to or coincident with
CS
transition LOW.
4. Transition is measured ±200mV from steady state voltage.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
6.42
5
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