74LVX32 Low Voltage Quad 2-Input OR Gate
May 1993
Revised March 1999
74LVX32
Low Voltage Quad 2-Input OR Gate
General Description
The LVX32 contains four 2-input OR gates. The inputs tol-
erate voltages up to 7V allowing the interface of 5V sys-
tems to 3V systems.
Features
s
Input voltage level translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX32M
74LVX32SJ
74LVX32MTC
Package Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Description
Pin Names
A
n
, B
n
O
n
Description
Inputs
Outputs
© 1999 Fairchild Semiconductor Corporation
DS011604.prf
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74LVX32
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
(I
CC
or I
GND
)
Storage Temperature (T
STG
)
Power Dissipation
±50
mA
−65°C
to
+150°C
180 mW
±25
mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−20
mA
−0.5V
to 7V
−0.5V
to
+7.0V
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Input Rise and Fall Time (∆t/∆V)
2.0V to 3.6V
0V to 5.5V
0V to V
CC
−40°C
to
+85°C
0 ns/V to 100 ns/V
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input
Voltage
V
IL
LOW Level Input
Voltage
V
OH
HIGH Level Output
Voltage
V
OL
LOW Level Output
Voltage
I
IN
I
CC
Input Leakage Current
Quiescent Supply Current
V
CC
2.0
3.0
3.6
2.0
3.0
3.6
2.0
3.0
3.0
2.0
3.0
3.0
3.6
3.6
1.9
2.9
2.58
0.0
0.0
0.1
0.1
0.36
±0.1
2.0
2.0
3.0
T
A
= +25°C
Min
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.48
0.1
0.1
0.44
±1.0
20
µA
µA
V
V
IN
=
V
IL
or V
IH
V
Typ
Max
T
A
= −40°C
to
+85°C
Min
1.5
2.0
2.4
0.5
0.8
0.8
V
IN
=
V
IL
or V
IH
I
OH
= −50 µA
I
OH
= −50 µA
I
OH
= −4
mA
I
OL
=
50
µA
I
OL
=
50
µA
I
OL
=
4 mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
V
V
Max
Units
Conditions
Noise Characteristics
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
(Note 3)
V
CC
(V)
3.3
3.3
3.3
3.3
T
A
=
25°C
Typ
0.3
−0.3
Limit
0.5
−0.5
2.0
0.8
Units
V
V
V
V
C
L
(pF)
50
50
50
50
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
Note 3:
(Input t
r
=
t
f
=
3 ns)
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2
74LVX32
AC Electrical Characteristics
Symbol
t
PLH
t
PHL
Parameter
Propagation
Delay Time
3.3
±
0.3
t
OSLH
t
OSHL
Output to Output
Skew (Note 4)
2.7
3.3
V
CC
(V)
2.7
T
A
= +25°C
Min
Typ
5.8
8.3
4.4
6.9
Max
10.7
14.2
6.6
10.1
1.5
1.5
T
A
= −40°C
to
+85°C
Min
1.0
1.0
1.0
1.0
Max
12.5
16.0
7.5
11.5
1.5
1.5
ns
ns
Units
C
L
(pF)
15
50
15
50
50
Note 4:
Parameter guaranteed by design. t
OSLH
=
|t
PLHm
−
t
PLHn
|, t
OSHL
=
|t
PHLm
−
t
PHLn
|
Capacitance
Symbol
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (Note 5)
Note 5:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Parameter
Min
T
A
= +25°C
Typ
4
14
Max
10
T
A
= −40°C
to
+85°C
Min
Max
10
Units
pF
pF
3
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74LVX32
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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4
74LVX32 Low Voltage Quad 2-Input OR Gate
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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SEMICONDUCTOR CORPORATION. As used herein:
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1. Life support devices or systems are devices or systems
device or system whose failure to perform can be rea-
which, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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