SN54ABT16374, SN74ABT16374
16 BIT EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
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Members of the Texas Instruments
Widebus
Family
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 5 V, T
A
= 25°C
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (− 32-mA I
OH
,
64-mA I
OL
)
Packaged in Plastic 300-mil Shrink
Small-Outline Packages (DL) and 380-mil
Fine-Pitch Ceramic Flat Packages (WD)
Using 25-mil Center-to-Center Spacings
SN54ABT16374 . . . WD PACKAGE
SN74ABT16374 . . . DL PACKAGE
(TOP VIEW)
SCBS454 - APRIL 1991 - REVISED JULY 1993
description
The ’ABT16374 is a 16-bit edge-triggered D-type
flip-flop with 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK)
input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components
The output enable (OE) does not affect internal operations of the flip-flop. Old data can be retained or new data
can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT16374 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin
count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ABT16374 is characterized for operation over the full military temperature range of −55°C to 125°C.
The SN74ABT16374 is characterized for operation from − 40°C to 85°C.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
Copyright
1993, Texas Instruments Incorporated
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SCBS454 - APRIL 1991 - REVISED JULY 1993
SN54ABT16374, SN74ABT16374
16 BIT EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
H
CLK
↑
↑
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
logic symbol
†
1OE
1CLK
2OE
2CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2D
2
1EN
C1
2EN
logic diagram (positive logic)
1OE
1CLK
1
48
C1
C2
1D
2
1
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
To 7 Other Channels
2D1
36
2CLK
2OE
24
25
To 7 Other Channels
1D1
47
1D
2
1Q1
C1
1D
13
2Q1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
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SN54ABT16374, SN74ABT16374
16 BIT EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCBS454 - APRIL 1991 - REVISED JULY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, V
O
. . . . . . . . . . . . . −0.5 V to 5.5 V
Current into any output in the low state, I
O
: SN54ABT16374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT16374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Maximum power dissipation at T
A
= 55°C (in still air) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
SN54ABT16374
MIN
VCC
VIH
VIL
VI
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Outputs enabled
−55
0
4.5
2
0.8
VCC
−24
48
10
125
−40
0
MAX
5.5
SN74ABT16374
MIN
4.5
2
0.8
VCC
−32
64
10
85
MAX
5.5
UNIT
V
V
V
V
mA
mA
ns/V
°C
TA
Operating free-air temperature
NOTE 2: Unused or floating inputs must be held high or low.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
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•
3
SCBS454 - APRIL 1991 - REVISED JULY 1993
SN54ABT16374, SN74ABT16374
16 BIT EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5 V,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 0,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VI = VCC or GND
TEST CONDITIONS
II = −18 mA
IOH = − 3 mA
IOH = − 3 mA
IOH = − 24 mA
IOH = − 32 mA
IOL = 48 mA
IOL = 64 mA
VI = VCC or GND
VO = 2.7 V
VO = 0.5 V
VI or VO
≤
4.5 V
VO = 5.5 V
Outputs high
VO = 2.5 V
Outputs high
ICC
IO = 0,
Outputs low
Outputs disabled
−50
−100
TA = 25°C
MIN TYP† MAX
−1.2
2.5
3
2
2‡
0.55
0.55‡
±1
50
−50
±100
50
−180
2
67
2
1.5
3.5
9.5
−50
50
−180
2
67
2
1.5
−50
2.5
3
2
2
0.55
0.55
±1
50
−50
±1
50
−50
±100
50
−180
2
67
2
1.5
mA
pF
pF
mA
V
µA
µA
µA
µA
µA
mA
SN54ABT16374
MIN
MAX
−1.2
2.5
3
V
SN74ABT16374
MIN
MAX
−1.2
UNIT
V
VOH
VOL
II
IOZH
IOZL
IOFF
ICEX
IO§
∆I
CC¶
Ci
Co
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
† All typical values are at VCC = 5 V.
‡ On products compliant to MIL-STD-883, Class B, this parameter does not apply.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN
fclock
tw
tsu
th
Clock frequency
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
0
3.3
1.1
1.3
MAX
150
SN54ABT16374
MIN
0
3.3
1.1
1.3
MAX
150
SN74ABT16374
MIN
0
3.3
1.1
1.3
MAX
150
MHz
ns
ns
ns
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
•
•
SN54ABT16374, SN74ABT16374
16 BIT EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCBS454 - APRIL 1991 - REVISED JULY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
150
1.8
CLK
OE
OE
Q
Q
Q
2.7
1.4
1.7
2.2
2.3
4.3
4.5
3.6
3.5
5.4
4.6
5.4
5.6
4.8
4.6
8.4
7.7
TYP
MAX
SN54ABT16374
MIN
150
1.8
2.7
1.4
1.7
2.2
2.3
6.4
6.4
6.1
5.5
11
9.8
MAX
SN74ABT16374
MIN
150
1.8
2.7
1.4
1.7
2.2
2.3
6.2
5.9
5.7
5.3
10
8.7
ns
ns
ns
MAX
MHz
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
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