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74ALVCH162374T

产品描述ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, TSSOP-48
产品类别逻辑   
文件大小80KB,共10页
制造商ST(意法半导体)
官网地址http://www.st.com/
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74ALVCH162374T概述

ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, TSSOP-48

74ALVCH162374T规格参数

参数名称属性值
厂商名称ST(意法半导体)
零件包装代码TSSOP
包装说明TSSOP, TSSOP48,.3,20
针数48
Reach Compliance Codecompliant
系列ALVC/VCX/A
JESD-30 代码R-PDSO-G48
长度12.5 mm
负载电容(CL)50 pF
逻辑集成电路类型BUS DRIVER
最大频率@ Nom-Sup300000000 Hz
最大I(ol)0.012 A
位数8
功能数量2
端口数量2
端子数量48
最高工作温度125 °C
最低工作温度-55 °C
输出特性3-STATE WITH SERIES RESISTOR
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP48,.3,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法TAPE AND REEL
电源3.3 V
Prop。Delay @ Nom-Sup4.6 ns
传播延迟(tpd)6.5 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)1.65 V
标称供电电压 (Vsup)2.7 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
触发器类型POSITIVE EDGE
宽度6.1 mm
Base Number Matches1

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74ALVCH162374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
PRELIMINARY DATA
s
s
s
s
s
s
s
s
s
s
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
PD
= 4.6 ns (MAX.) at V
CC
= 3.0 to 3.6V
t
PD
= 5.4 ns (MAX.) at V
CC
= 2.3 to 2.7V
t
PD
= 6.5 ns (MAX.) at V
CC
= 1.65V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3.0V
|I
OH
| = I
OL
= 18mA (MIN) at V
CC
= 2.3V
|I
OH
| = I
OL
= 4mA (MIN) at V
CC
= 1.65V
BUS HOLD PROVIDED ON DATA INPUTS
26Ω SERIE RESISTORS IN OUTPUTS
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16374
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
T&R
74ALVCH162374T
PIN CONNECTION
DESCRIPTION
The 74ALVCH162374 is a low voltage CMOS 16
BIT D-TYPE LATCH with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and five-layer metal wiring C
2
MOS
technology. It is ideal for low power and very high
speed 1.65 to 3.6V applications; it can be
interfaced to 3.6V signal environment for both
inputs and outputs.
These flip-flops are controlled by two clock inputs
(nCK) and two output enable inputs (nOE).
On the positive transition of the (nCK), the nQ
outputs will be set to the logic state that were
setup at the nD inputs.
While the (nOE) input is low, the outputs (nQ) will
be in a normal state (HIGH or LOW logic level)
and while high level the outputs will be in a high
impedance state.
Any output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.The device circuits is
including 26Ω series resistance in the outputs.
These resistors permit to reduce line noise in high
speed applications.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
October 2002
1/10
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.

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