74VHC123A Dual Retriggerable Monostable Multivibrator
May 2007
74VHC123A
Dual Retriggerable Monostable Multivibrator
Features
■
High Speed: t
PD
=
8.1ns (Typ.) at T
A
=
25°C
■
Low Power Dissipation: I
CC
=
4µA (Max) at T
A
=
25°C
■
Active State: I
CC
=
600µA (Max.) at T
A
=
25°C
■
High Noise Immunity: V
NIH
=
V
NIL
=
28% V
CC
(Min.)
■
Power down protection is provided on all inputs
■
Pin and function compatible with 74HC123A
tm
General Description
The VHC123A is an advanced high speed CMOS
Monostable Multivibrator fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while main-
taining the CMOS low power dissipation. Each multi-
vibrator features both a negative, A, and a positive, B,
transition triggered input, either of which can be used as
an inhibit input. Also included is a clear input that when
taken low resets the one-shot. The VHC123A can be
triggered on the positive transition of the clear while A is
held low and B is held high. The output pulse width is
determined by the equation: PW
=
(R
x
)(C
x
); where PW
is in seconds, R is in ohms, and C is in farads.
Limits for R
x
and C
x
are:
External capacitor, C
x
: No limit
External resistors, R
x
: V
CC
=
2.0V, 5 k
Ω
min
V
CC
>
3.0V, 1 k
Ω
min
An input protection circuit ensures that 0 to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Ordering Information
Order Number
74VHC123AM
74VHC123ASJ
74VHC123AMTC
Package
Number
M16A
M16D
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number.
©1993 Fairchild Semiconductor Corporation
74VHC123A Rev. 1.2
www.fairchildsemi.com
74VHC123A Dual Retriggerable Monostable Multivibrator
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
A
B
CLR
C
x
R
x
Q, Q
Description
Trigger Inputs (Negative Edge)
Trigger Inputs (Positive Edge)
Reset Inputs
External Capacitor
External Resistor
Outputs
Truth Table
Inputs
A
X
H
L
L
X
H
X
L
L
H
Outputs
CLR
H
H
H
H
L
L
H
H
B
H
L
X
Q
Q
Function
Output Enable
Inhibit
Inhibit
Output Enable
Output Enable
Reset
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
=
HIGH-to-LOW Transition
=
LOW-to-HIGH Transition
X
=
Don't Care
©1993 Fairchild Semiconductor Corporation
74VHC123A Rev. 1.2
www.fairchildsemi.com
2
74VHC123A Dual Retriggerable Monostable Multivibrator
Block Diagrams
Note A:
C
x
, R
x
, D
x
are external Capacitor, Resistor, and Diode, respectively.
Note B:
External clamping diode, D
x
;
External capacitor is charged to V
CC
level in the wait state, i.e. when no trigger is applied.
If the supply voltage is turned off, C
x
discharges mainly through the internal (parasitic) diode. If C
x
is sufficiently large
and V
CC
drops rapidly, there will be some possibility of damaging the IC through in rush current or latch-up. If the
capacitance of the supply voltage filter is large enough and V
CC
drops slowly, the in rush current is automatically
limited and damage to the IC is avoided.
The maximum value of forward current through the parasitic diode is ±20mA. In the case of a large Cx, the limit of fall
time of the supply voltage is determined as follows:
t
f
≥
(V
CC
–0.7) C
x
/ 20mA
(t
f
is the time between the supply voltage turn off and the supply voltage reaching 0.4 V
CC
)
In the event a system does not satisfy the above condition, an external clamping diode (D
x
) is needed to protect the IC
from rush current.
©1993 Fairchild Semiconductor Corporation
74VHC123A Rev. 1.2
www.fairchildsemi.com
3
74VHC123A Dual Retriggerable Monostable Multivibrator
System Diagram
Timing Chart
©1993 Fairchild Semiconductor Corporation
74VHC123A Rev. 1.2
www.fairchildsemi.com
4
74VHC123A Dual Retriggerable Monostable Multivibrator
Functional Description
1. Stand-by State
The external capacitor (C
x
) is fully charged to V
CC
in
the Stand-by State. That means, before triggering,
the Q
P
and Q
N
transistors which are connected to the
R
x
/C
x
node are in the off state. Two comparators that
relate to the timing of the output pulse, and two refer-
ence voltage supplies turn off. The total supply cur-
rent is only leakage current.
2. Trigger Operation
Trigger operation is effective in any of the following
three cases. First, the condition where the A input is
LOW, and B input has a rising signal; second, where
the B input is HIGH, and the A input has a falling sig-
nal; and third, where the A input is LOW and the B
input is HIGH, and the CLR input has a rising signal.
After a trigger becomes effective, comparators C
1
and C
2
start operating, and Q
N
is turned on. The
external capacitor discharges through Q
N
. The volt-
age level at the R
x
/C
x
node drops. If the R
x
/C
x
volt-
age level falls to the internal reference voltage V
ref
L,
the output of C
1
becomes LOW. The flip-flop is then
reset and Q
N
turns off. At that moment C
1
stops but
C
2
continues operating.
After Q
N
turns off, the voltage at the R
x
/C
x
node
starts rising at a rate determined by the time constant
of external capacitor C
x
and resistor R
x
.
Upon triggering, output Q becomes HIGH, following
some delay time of the internal F/F and gates. It stays
HIGH even if the voltage of R
x
/C
x
changes from fall-
ing to rising. When R
x
/C
x
reaches the internal refer-
ence voltage V
ref
H, the output of C
2
becomes LOW,
the output Q goes LOW and C
2
stops its operation.
That means, after triggering, when the voltage level
of the R
x
/C
x
node reaches V
ref
H, the IC returns to its
MONOSTABLE state.
With large values of C
x
and R
x
, and ignoring the dis-
charge time of the capacitor and internal delays of
the IC, the width of the output pulse, t
W
(OUT), is as
follows:
t
W
(OUT)
=
1.0 C
x
R
x
3. Retrigger operation (74VHC123A)
When a new trigger is applied to either input A or B
while in the MONOSTABLE state, it is effective only if
the IC is charging C
x
. The voltage level of the R
x
/C
x
node then falls to V
ref
L level again. Therefore the Q
output stays HIGH if the next trigger comes in before
the time period set by C
x
and R
x
.
If the new trigger is very close to a previous trigger,
such as an occurrence during the discharge cycle, it
will have no effect.
The minimum time for a trigger to be effective 2nd
trigger, t
RR
(Min), depends on V
CC
and C
x
.
4. Reset Operation
In normal operation, the CLR input is held HIGH. If
CLR is LOW, a trigger has no affect because the Q
output is held LOW and the trigger control F/F is
reset. Also, Q
p
turns on and C
x
is charged rapidly to
V
CC
.
This means if CLR is set LOW, the IC goes into a wait
state.
©1993 Fairchild Semiconductor Corporation
74VHC123A Rev. 1.2
www.fairchildsemi.com
5
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