74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25
Ω
Series Resistors in the Outputs
July 2007
74LVTH162374
Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE
Outputs and 25
Ω
Series Resistors in the Outputs
Features
■
Input and output interface capability to systems at 5V
■
■
■
■
tm
General Description
The LVTH162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus
oriented applications. The device is byte controlled. A
buffered clock (CP) and Output Enable (OE) are com-
mon to each byte and can be shorted together for full
16-bit operation.
The LVTH162374 is designed with equivalent 25
Ω
series resistance in both the HIGH and LOW states of
the output. This design reduces line noise in applications
such as memory address drivers, clock drivers, and bus
transceivers/transmitters.
The LVTH162374 data inputs include bushold, eliminat-
ing the need for external pull-up resistors to hold unused
inputs.
These flip-flops are designed for low-voltage (3.3V) V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH162374 is fabri-
cated with an advanced BiCMOS technology to achieve
high speed operation similar to 5V ABT while maintain-
ing a low power dissipation.
■
■
■
■
V
CC
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power Up/Power Down high impedance provides
glitch-free bus loading
Outputs include equivalent series resistance of 25
Ω
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
Functionally compatible with the 74 series 16374
Latch-up performance exceeds 500mA
ESD performance:
– Human-body model > 2000V
– Machine model > 200V
– Charged-device model > 1000V
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Information
Order Number
74LVTH162374GX
(1)
74LVTH162374MEA
74LVTH162374MEX
74LVTH162374MTD
74LVTH162374MTX
Package
Number
BGA54A
(Preliminary)
MS48A
MS48A
MTD48
MTD48
Pb-Free
Yes
Yes
Yes
Yes
Yes
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA),
JEDEC MO-205, 5.5mm Wide
48-Lead Small Shrink Outline Package
(SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Small Shrink Outline Package
(SSOP), JEDEC MO-118, 0.300" Wide
Supplied As
Tape and Reel
Tubes
Tape and Reel
48-Lead Thin Shrink Small Outline Package
Tubes
(TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package
Tape and Reel
(TSSOP), JEDEC MO-153, 6.1mm Wide
Notes:
1. BGA package available in Tape and Reel only.
©2000 Fairchild Semiconductor Corporation
74LVTH162374 Rev. 1.0.0
www.fairchildsemi.com
74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25
Ω
Series Resistors in the Outputs
Connection Diagrams
Pin Assignments for SSOP and TSSOP
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
O
0
O
2
O
4
O
6
O
8
O
10
O
12
O
14
O
15
2
NC
O
1
O
3
O
5
O
7
O
9
O
11
O
13
NC
3
OE
1
NC
V
CC
GND
GND
GND
V
CC
NC
OE
2
4
CP
1
NC
V
CC
GND
GND
GND
V
CC
NC
CP
2
5
NC
I
1
I
3
I
5
I
7
I
9
I
11
I
13
NC
6
I
0
I
2
I
4
I
6
I
8
I
10
I
12
I
14
I
15
Logic Symbol
Truth Tables
Pin Assignment for FPGA
Inputs
CP
1
OE
1
L
L
L
X
L
H
Outputs
I
0
–I
7
H
L
X
X
O
0
–O
7
H
L
O
o
Z
Inputs
CP
2
OE
2
L
L
(Top Thru View)
Outputs
I
8
–I
15
H
L
X
X
O
8
–O
15
H
L
O
o
Z
L
X
L
H
Pin Description
Pin Name
OE
n
CP
n
I
0
–I
15
O
0
–O
15
NC
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
3-STATE Outputs
No Connect
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
O
o
= Previous O
o
before LOW-to-HIGH of CP
©2000 Fairchild Semiconductor Corporation
74LVTH162374 Rev. 1.0.0
www.fairchildsemi.com
2
74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25
Ω
Series Resistors in the Outputs
Functional Description
The LVTH162374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte
functioning identically, but independent of the other. The
control pins can be shorted together to obtain full 16-bit
operation. Each byte has a buffered clock and buffered
Output Enable common to all flip-flops within that byte.
The description which follows applies to each byte. Each
flip-flop will store the state of their indi-vidual D-type
inputs that meet the setup and hold time requirements
on the LOW-to-HIGH Clock (CP
n
) transition. With the
Output Enable (OE
n
) LOW, the contents of the flip-flops
are available at the outputs. When OE
n
is HIGH, the
outputs go to the high impedance state. Operation of the
OE
n
input does not affect the state of the flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate
propagation delays.
©2000 Fairchild Semiconductor Corporation
74LVTH162374 Rev. 1.0.0
www.fairchildsemi.com
3
74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25
Ω
Series Resistors in the Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Conditions
Value
-0.5 to +4.6
-0.5 to +7.0
Units
V
V
V
mA
mA
mA
mA
mA
°C
Output in 3-STATE
Output in HIGH or LOW State
(2)
V
I
< GND
V
O
< GND
V
O
> V
CC
Output at HIGH State
V
O
> V
CC
Output at LOW State
-0.5 to +7.0
-0.5 to +7.0
-50
-50
64
128
±64
±128
-65 to +150
Note:
2. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
I
OH
I
OL
T
A
∆t/∆V
Supply Voltage
Input Voltage
Parameter
Min.
2.7
0
Max.
3.6
5.5
-12
12
Units
V
V
mA
mA
°C
ns/V
HIGH Level Output Current
LOW Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
= 0.8V–2.0V, V
CC
= 3.0V
-40
0
85
10
©2000 Fairchild Semiconductor Corporation
74LVTH162374 Rev. 1.0.0
www.fairchildsemi.com
4
74LVTH162374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25Ω Series Resistors in the Outputs
DC Electrical Characteristics
T
A
= -40°C to
+85°C
Symbol
V
IK
V
IH
V
IL
V
OH
V
OL
I
I(HOLD)
I
I(OD)
I
I
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Bushold Input Minimum Drive
Bushold Input Over-Drive Current
to Change State
Input Current
Control Pins
Data Pins
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
3.0
2.7
3.0
3.0
3.0
3.6
Conditions
I
I
= -18mA
V
O
≤
0.1V or
V
O
≥
V
CC
– 0.1V
I
OH
= -100µA
I
OH
= -12mA
I
OL
= 100µA
I
OL
= 12mA
V
I
= 0.8V
V
I
= 2.0V
(3)
(4)
MIn.
2.0
Max. Units
-1.2
0.8
V
V
V
V
0.2
0.8
V
µA
µA
10
±1
-5
1
±100
±100
-5
5
10
0.19
5
0.19
0.19
0.2
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
µA
V
CC
– 0.2V
2.0
75
-75
500
-500
V
I
= 5.5V
V
I
= 0V or V
CC
V
I
= 0V
V
I
= V
CC
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
+
I
CCH
I
CCL
I
CCZ
I
CCZ
+
∆I
CC
Power Off Leakage Current
Power Up/Down 3-STATE Output
Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
Increase in Power Supply Current
(5)
0
0–1.5
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0V
≤
V
I
or V
O
≤
5.5V
V
O
= 0.5V to 3.0V,
V
I
= GND or V
CC
V
O
= 0.5V
V
O
= 3.0V
V
CC
< V
O
≤
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
V
CC
≤
V
O
≤
5.5V,
Outputs Disabled
One Input at V
CC
– 0.6V
Other Inputs at V
CC
or GND
Notes:
3. An external driver must source at least the specified current to switch from LOW-to-HIGH.
4. An external driver must sink at least the specified current to switch from HIGH-to-LOW.
5. This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
©2000 Fairchild Semiconductor Corporation
74LVTH162374 Rev. 1.0.0
www.fairchildsemi.com
5
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