TN2124
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
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Free from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C
ISS
and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode
High input impedance and high gain
Complementary N- and P-channel devices
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Applications
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Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Ordering Information
BV
DSS
/BV
DGS
(V)
Pin Configuration
Package Option
TO-236AB (SOT-23)
TN2124K1-G
R
DS(ON)
max
(Ω)
V
GS(th)
max
(V)
DRAIN
240
15
2.0
-G indicates package is RoHS compliant (‘Green’)
SOURCE
GATE
TO-236AB (SOT-23) (K1)
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Soldering temperature*
Value
BV
DSS
BV
DGS
±20V
-55
O
C to +150
O
C
300 C
O
Product Marking
N1CW
W = Code for week sealed
TO-236AB (SOT-23) (K1)
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
TN2124
Thermal Characteristics
Package
TO-236AB (SOT-23) (K1)
(continuous)
(mA)
I
D
(*)
(pulsed)
(mA)
I
D
Power Dissipation
@T
A
= 25
O
C
(W)
θ
jc
( C/W)
O
θ
ja
( C/W)
O
I
DR(*)
(mA)
I
DRM
(mA)
134
250
0.36
200
350
134
250
Notes:
* I
D
(continuous) is limited by max rated T
j
.
Electrical Characteristics
(@25 C unless otherwise specified)
O
Sym
BV
DSS
V
GS(th)
ΔV
GS(th)
I
GSS
I
DSS
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
Parameter
Drain-to-source breakdown voltage
Gate threshold voltage
Change in V
GS(th)
with temperature
Gate body leakage
Zero gate voltage drain current
ON-state drain current
Static drain-to-source ON-state resistance
Change in R
DS(ON)
with temperature
Forward transductance
Input capacitance
Common source output capacitance
Reverse transfer capacitance
Turn-ON delay time
Rise time
Turn-OFF delay time
Fall time
Diode forward voltage drop
Reverse recovery time
Min
240
0.8
-
-
-
-
140
-
-
-
100
-
-
-
-
-
-
-
-
-
Typ
-
-
-
0.1
-
-
-
-
-
0.7
170
38
9.0
3.0
4.0
2.0
7.0
9.0
-
400
Max
-
2.0
-5.5
100
1.0
100
-
30
15
1.0
-
50
15
5.0
7.0
5.0
10
12
1.8
-
Units
V
V
nA
µA
µA
mA
Ω
Ω
%/
O
C
Conditions
V
GS
= 0V, I
D
= 1.0mA
V
GS
= V
DS
, I
D
= 1.0mA
V
GS
= ± 20V, V
DS
= 0V
V
GS
= 0V, V
DS
= Max Rating
V
GS
= 0V, V
DS
= 0.8 Max Rat-
ing, T
A
= 125°C
V
GS
= 4.5V, V
DS
= 25V
V
GS
= 3.0V, I
D
= 25mA
V
GS
= 4.5V, I
D
= 120mA
V
GS
= 4.5V, I
D
= 120mA
V
GS
= 0V,
V
DS
= 25V,
f = 1.0MHz
V
DD
= 25V,
I
D
= 140mA,
R
GEN
= 25Ω
mV/
O
C V
GS
= V
DS
, I
D
= 1.0mA
mmho V
DS
= 25V, I
D
= 120mA
pF
ns
V
ns
V
GS
= 0V, I
SD
= 120mA
V
GS
= 0V, I
SD
= 120mA
Notes:
(1) All D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
(2) All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
V
DD
10V
90%
INPUT
0V
10%
t
(ON)
PULSE
GENERATOR
t
(OFF)
t
r
t
d(OFF)
t
F
R
L
OUTPUT
R
GEN
t
d(ON)
V
DD
10%
10%
INPUT
D.U.T.
OUTPUT
0V
90%
90%
2
TN2124
Typical Performance Curves
Output Characteristics
2.0
1.0
Saturation Characteristics
1.6
0.8
V
GS
= 10V
8V
I
D
(amperes)
6V
4V
3V
1.2
I
D
(amperes)
V
GS
= 10V
8V
6V
0.6
0.8
4V
0.4
3V
0.4
2V
0
0
10
20
30
40
50
0
0
2
4
6
8
10
0.2
2V
V
DS
(volts)
Transconductance vs. Drain Current
1.0
V
DS
= 25V
0.8
1.6
2.0
V
DS
(volts)
Power Dissipation vs. Temperature
G
FS
(siemens)
0.4
-55
O
C
P
D
(watts)
0.6
1.2
0.8
0.2
TA= 125
O
C
0
0
0.2
0.4
0.6
0.8
1.0
25
O
C
0.4
SOT-23
0.0
0
25
50
75
100
125
150
I
D
(amperes)
Maximum Rated Safe Operating Area
10
1.0
TA= 25
O
C
T
A
(
O
C)
Thermal Response Characteristics
Thermal Resistance (normalized)
0.8
I
D
(amperes)
1.0
SOT-23 (pulsed)
0.6
SOT-23
T
A
= 25
O
C
P
D
= 0.36W
0.4
0.1
0.2
SOT-23 (DC)
0.01
0
10
100
1000
0
0.001
0.01
0.1
1
10
V
DS
(volts)
t
p
(seconds)
3
TN2124
Typical Performance Curves
(cont.)
BV
DSS
Variation with Temperature
50
1.1
40
On-Resistance vs. Drain Current
V
GS
= 3V
BV
DSS
(normalized)
R
DS(ON)
(ohms)
30
1.0
20
V
GS
= 4.5V
10
0.9
0
-50
0
50
100
150
0
0.2
0.4
0.6
0.8
1.0
T
j
( C)
Transfer Characteristics
1.0
1.4
0.8
O
I
D
(amperes)
V
TH
and R
DS
Variation with Temperature
2.0
R
DS(ON)
@ 4.5V, 120mA
1.6
T
A
= -55 C
O
I
D
(amperes)
25
O
C
0.6
1.2
1.2
1.0
0.8
0.8
0.4
V
DS
= 25V
0.2
0.6
0
0
2
4
6
8
10
-50
0
V
GS(th)
@ 1mA
0.4
0
50
100
150
V
GS
(volts)
Capacitance vs. Drain-to-Source Voltage
100
10
T
j
(
O
C)
Gate Drive Dynamic Characteristics
8
75
C (picofarads)
V
GS
(volts)
f = 1MHz
50
6
4
C
ISS
25
V
DS
= 10V
100pF
V
DS
= 40V
2
C
RSS
0
0
10
20
C
OSS
0
30
40
0
32 pF
0.2
0.4
0.6
0.8
1.0
V
DS
(volts)
Q
G
(nanocoulombs)
4
R
DS(ON)
(normalized)
125
O
C
V
GS(th)
(normalized)
TN2124
3-Lead TO-236AB (SOT-23) Package Outline (K1)
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch
D
3
E1 E
0.25
Gauge
Plane
1
e
e1
2
b
L
L1
Seating
Plane
Top View
A
View B
View B
A
A2
Seating
Plane
A1
Side View
A
View A-A
Symbol
MIN
Dimension
(mm)
NOM
MAX
A
0.89
-
1.12
A1
0.01
-
0.10
A2
0.88
0.95
1.02
b
0.30
-
0.50
D
2.80
2.90
3.04
E
2.10
-
2.64
E1
1.20
1.30
1.40
e
0.95
BSC
e1
1.90
BSC
L
0.40
0.50
0.60
L1
0.54
REF
θ
0
O
-
8
O
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to
http://www.supertex.com/packaging.html.)
Doc.# DSFP-TN2124
B101107
5
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